Simulations Lab 3 ECE 200

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Dec 6, 2023

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ECE-200: Digital Logic Design Laboratory Assignment 3 In this lab you will learn how to write hierarchical VHDL code . In hierarchical VHDL code, you define entities that you can then deploy as reusable components in more complex designs. This concept may be familiar to you if you have used an object oriented programming language. The basic idea is very similar to instantiating an object from a class in Python, C++, or Java, for example. Let’s look at a simple example. First, we’ll define a 2-input gate and a 2-input gate with the intention of reusing them in just a moment as components in a more complicated design. : 1 2 ( 3 A, B : ; 4 C : 5 ); 6 ; 7 8 9 ( 10 A, B : ; 11 C : 12 ); 13 ; 14 15 16 17 C <= A B; 18 ; 19 20 21 22 C <= A B; 23 ; Excellent! We now have a 2-input gate component named and a 2-input gate component named . Let’s use these to implement the following simple circuit shown in Fig. 1: W P Q X Y Z F AND2 u1 u3 u2 AND2 OR2 Fig. 1: Schematic of a simple entity that reuses our and entities. 1 Shackleford
ECE-200: Digital Logic Design Lab 3 Let’s implement the schematic shown in Fig. 1 as a new entity in our VHDL code named that has four inputs ( , , , & ) and one output ( ). The architecture for will reuse our and entities by instantiating them. We will then use signals , which you can think of as “wires,” to make connections between our and instances. (continued) : 25 26 ( 27 W, X, Y, Z : ; 28 F : 29 ); 30 ; 31 32 33 34 -- make AND2 an available component 35 36 ( 37 A, B : ; 38 C : 39 ); 40 ; 41 42 -- make OR2 an available component 43 44 ( 45 A, B : ; 46 C : 47 ); 48 ; 49 50 -- make two "wires" named P and Q 51 P, Q : ; 52 53 54 u1 : AND2 (W, X, P); -- instantiate AND2 & connect W->A, X->B, and C->P 55 u2 : AND2 (Y, Z, Q); -- instantiate AND2 & connect Y->A, Z->B, and C->Q 56 u3 : OR2 (P, Q, F); -- instantiate OR2 & connect P->A, Q->B, and C->F 57 58 ; Notice how this definition of the architecture is different than what we are used to. Instead of defining its behavior using keywords like , , and , we defined its structure by placing and components that we then connected together using signals (i.e. wires). If you compile this example program and simulate it, you will see the output shown in Fig. 2, which matches our expectations. Fig. 2: Simulation output of the entity . Notice how the signals and (the outputs from our two gates) can also be added to the wave display for easier analysis of our circuit’s behavior. 2 Shackleford
ECE-200: Digital Logic Design Lab 3 Part I (25pts) Here you will practice implementing a circuit using hierarchical VHDL . Let’s start by implementing some reusable components. Create a new project in ModelSim, create a new VHDL file, and define the following entities: 1. Define a 4-input gate entity named 2. Define a 6-input gate entity named 3. Define a 1-input gate entity named Now that you have these entities defined, it’s time to specify their architectures . Write a behavior style architecture block for each of your three entities. In each architecture block, choose from the operator keywords , , and – use the ones necessary to properly implement your , , and architectures. TIP If you are having trouble, refer to the example on Page 1 where we implemented the behavior style architectures for and . Also, recall from Lecture 4 that multiple , , and operators may be used together with multiple variables on the right-hand side of the operator in an assignment expression. Have you finished implementing your , , and gates? Great! Did you simulate them to make sure they are working like you expect? The TAs aren’t not going ask to see your simulations to make sure that you did , in fact, simulate these three gates, but it’s probably a really good idea to take a few moments to simulate them real quick. Since you are about to build a fairly large circuit using these gates, making sure they all work correctly by simulating them first may save you from a few headaches in a moment. Alright, now that you have your , and gates, it’s time to build something with them. Specifi- cally, you are going to use your new gates to implement a circuit whose output is described by the following Sum-Of-Minterms expression: F = (4 , 5 , 6 , 12 , 13 , 14) In your VHDL file, add an entity named with four inputs ( , , , & ) and one output ( ). Now create an block for your entity where you will directly implement the structure of the circuit described by the above Sum-Of-Minterms expression (do not simplify it yet!). To do this, you will need to use 11 instances (total) of the gates you just created as well as 10 signals to connect everything together. To help get you started, we recommend naming your signals: , , , , , , , , , and . TIP If you are having trouble, refer to the example on Page 2 where we implemented the structure style architecture for the entity. What you need to do here is very similar, but the circuit you are defining the structure for is a bit larger. It may help to draw the circuit you are going to implement, like we did in Fig. 1. Simulate your completed circuit with all possible input combinations (as you did in Lab 2). Building a truth table for the boolean expression you are implementing will allow you to easily identify if your implementation is correct. When your simulation matches your truth table, you can be confident in the correctness of your work. Show your code and working simulation to the TA for credit! 3 Shackleford
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ECE-200: Digital Logic Design Lab 3 Part II (25pts) Now that you have directly implemented and simulated the following Sum-Of-Minterms expression in Part I : F = (4 , 5 , 6 , 12 , 13 , 14) it is time to simplify this equation to yield a minimal circuit. Use a Karnaugh Map (i.e. K-Map) to simplify this equation. Write the simplified equation below and have it checked by the TA: Now that you have a simplified boolean equation, you can implement a circuit that is functionally equivalent to the one you implemented in Part I , but using far fewer gates. Implement this minimal circuit using a hierarchical VHDL design, similar to what you did in Part I of this lab. You will need to create two entities ( and ) that have behavioral architectures. You will also need to create an entity for your minimal circuit named that will have a structural architecture. Once you have completed your design, simulate it for all possible input combinations and compare it to the simulation output you produced in Part I . You will know that you successfully implemented the minimal circuit if the two simulation outputs match. TIP When you define your entity, be sure it has all four inputs ( , , , and ). Even though you may not need to connect some of these inputs to gates, they are still inputs to the device you are modeling. Including them will make comparing the simulation output of your circuit to the simulation output of your circuit much easier. Show your code and working simulation to the TA for credit! DUE DATE October 27 (in lab) You have 2 lab sessions to complete this lab. You may continue to work on the lab assignment between lab sessions. You must have all of your work checked off by the TA for credit by the end of lab on 10 / 27 /202 3 . 4 Shackleford