Simulations Lab 3 ECE 200
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ECE-200: Digital Logic Design
Laboratory Assignment 3
In this lab you will learn how to write
hierarchical VHDL code
. In hierarchical VHDL code, you define
entities that you can then deploy as reusable components in more complex designs. This concept may be
familiar to you if you have used an object oriented programming language. The basic idea is very similar to
instantiating an object from a class in Python, C++, or Java, for example.
Let’s look at a simple example. First, we’ll define a 2-input
gate and a 2-input
gate with the intention
of reusing them in just a moment as components in a more complicated design.
:
1
2
(
3
A, B
:
;
4
C
:
5
);
6
;
7
8
9
(
10
A, B
:
;
11
C
:
12
);
13
;
14
15
16
17
C
<=
A
B;
18
;
19
20
21
22
C
<=
A
B;
23
;
Excellent! We now have a 2-input
gate component named
and a 2-input
gate component named
. Let’s use these to implement the following simple circuit shown in Fig. 1:
W
P
Q
X
Y
Z
F
AND2
u1
u3
u2
AND2
OR2
Fig. 1:
Schematic of a simple entity that reuses our
and
entities.
1
Shackleford
ECE-200: Digital Logic Design
Lab 3
Let’s implement the schematic shown in Fig. 1 as a new
entity
in our VHDL code named
that
has four inputs ( ,
,
, &
) and one output ( ). The
architecture
for
will reuse our
and
entities by
instantiating
them. We will then use
signals
, which you can think of as “wires,” to make
connections between our
and
instances.
(continued)
:
25
26
(
27
W, X, Y, Z
:
;
28
F
:
29
);
30
;
31
32
33
34
-- make AND2 an available component
35
36
(
37
A, B
:
;
38
C
:
39
);
40
;
41
42
-- make OR2 an available component
43
44
(
45
A, B
:
;
46
C
:
47
);
48
;
49
50
-- make two "wires" named P and Q
51
P, Q
:
;
52
53
54
u1
:
AND2
(W, X, P);
-- instantiate AND2 & connect W->A, X->B, and C->P
55
u2
:
AND2
(Y, Z, Q);
-- instantiate AND2 & connect Y->A, Z->B, and C->Q
56
u3
:
OR2
(P, Q, F);
-- instantiate OR2
& connect P->A, Q->B, and C->F
57
58
;
Notice how this definition of the architecture is different than what we are used to.
Instead of defining
its
behavior
using keywords like
,
, and
, we defined its
structure
by placing
and
components that we then connected together using signals (i.e. wires). If you compile this example program
and simulate it, you will see the output shown in Fig. 2, which matches our expectations.
Fig. 2:
Simulation output of the entity
. Notice how the signals
and
(the outputs from our two
gates) can also be added to the wave display for easier analysis of our circuit’s behavior.
2
Shackleford
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