Final F20 Solution

© EECS 370, University of Michigan EECS 370 Final Exam Fall 2020 Solution This exam is presented with modifications. This exam was originally released through gradescope in a virtual semester. Some comments have been added to reflect modifications for a paper exam. Question 1: Short Answer T/F Specify whether statements a-j are True or False. (On the exam a random set of 10 questions was chosen) True/False a. There are 32-bit two's complement integers that cannot be represented in a 32-bit IEEE-754 single precision number. T b. Deeper pipelines will generally have a shorter clock period. T c. It is possible for a write-back and a write-through cache to perform the same number of writes. T d. For a given cache size and block size, increasing associativity will reduce cache misses for any program. F e. Resolving data hazards with detect and stall and control hazards with speculate and squash will produce the least number of errors T f. Direction prediction for jalr is worse than beq. F g. Fetch stage can read an instruction from memory when there is a lw/sw in the MEM stage. F h. Physical memory and disk is typically large enough to hold all of a process’s virtual memory. F i. DRAM is a non-volatile memory. F j. You have scrolled through the whole exam to understand point distribution and allocate your time as such. T k. If a program accesses the same cache block repeatedly, it is has higher temporal locality T

2 l. Multi-level page tables will always take up less space than single- level page tables. F m. Cache is about the same size as main memory. F n. Dirty bits are needed for write-through caches but not for write- back caches. F o. Assuming we have an allocate-on-write store policy, an infinitely large cache would have only one miss per cache block. T p. The number of block offset bits is equal to log 2 (size of the cache). F q. For a given cache configuration, a write-through cache may write fewer bytes to memory than a write-back cache running the same program. T r. Virtual memory offers the illusion of infinite memory space. T s. A disadvantage of having a deeper pipeline is that there will be more stalls from data and control hazards. T t. For a given cache size and block size, increasing associativity will reduce tag size. F

4 6 7 8 9 10 11 12 13 14 end neg1 pos1 four count add sw beq beq halt .fill .fill .fill .fill 1 0 0 0 3 2 1 0 1 count end loop -1 1 4 0 V3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 loop end neg1 pos1 four count lw lw lw lw add add sw beq beq halt .fill .fill .fill .fill 0 0 0 0 4 3 0 0 0 1 2 3 4 2 1 4 3 0 neg1 pos1 four count 42q 3 count end loop -1 1 4 0 V4 1 2 3 4 5 6 7 loop lw lw lw lw add add sw 0 0 0 0 2 1 0 1 2 3 4 4 3 2 six count neg1 pos1 2 1 count

5 8 9 10 11 12 13 14 end neg1 pos1 six count beq beq halt .fill .fill .fill .fill 0 0 1 0 end loop -1 1 6 0 V5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 loop end neg1 pos1 five count lw lw lw lw add add sw beq beq halt .fill .fill .fill .fill 0 0 0 0 2 1 0 0 0 1 2 3 4 4 3 2 1 0 five count neg1 pos1 2 1 count end loop -1 1 5 0 A. Select all registers that cause a RAW data hazard in a detect and stall pipeline. a. reg0 b. reg1 c. reg2 d. reg3 e. reg4 f. reg5 g. reg6 Lines 4-5 need 2 stalls Lines 5-7 need 1 stall V1: reg4 V2: reg4 and reg2

7 Consider the LC2K pipeline with the following change: ● Execution (EX) stage split into two (EX1, EX2). ● EX1 calculates the branch destination and performs the equality check of beq . ● EX2 utilizes the ALU for the add/nor/lw/sw instructions. EX2 also updates the PC for branches, if necessary. ● Assume all values are forwarded to EX1. Control hazards resolved using speculate and squash , where branches are predicted to be not-taken . Data hazards resolved using detect and forward . Consider the following LC2K program: 1. lw 0 1 0 2. lw 0 2 1 3. beq 2 2 1 4. add 1 1 1 5. add 1 2 1 6. add 2 2 3 7. halt You are a hacker that has somehow managed to take the following snapshot of the pipeline registers while executing the above program before cycle C . Your goal is to determine a secret number that is stored in virtual memory address 0 . IF/ID ID/EX1 instr: X X X X instr: X X X X PC+1: X PC+1: X regA val: regB val: offset: EX1/EX2 EX2/MEM Instr: (A) _ X X X Instr: (B) _ _ _ _ PC Plus 1: X AluResult: 36 regA val: X regB val: (C) _ regB val: X branchTarget: X MEM/WB WB/END Instr: (D) add _ _ _ instr: noop X X X writeData: 60 writeData: X

8 List all the data hazards. Specify each data hazard in the following format: line #X, line #Y, number-of-cycles-stalled where X, Y are lines in the LC2K program that have a RAW dependency causing the data hazard. Line #2, Line #3, 2 cycles List all the control hazards. Specify each control hazard in the following format: line #X, number-of-cycles-stalled where X is a line in the LC2K program that causes the control hazard. Line #3, 3 cycles How many instructions does the LC2K program execute? (enter only the number here) 6 instructions Fill in the missing blanks in the highlighted boxes from the pipeline snapshot above. EX1/EX2 - (A): halt EX2/MEM - (B): add 2 2 3 EX2/MEM - (C): 18 MEM/WB - (D): (add) 1 2 1 If we assume that the first instruction of the program is in the fetch stage during Cycle 0, before which cycle (C) was the pipeline snapshot taken? (show your work) 13 2 data hazard stalls + 3 control hazard stalls + 6 instructions + 2 cycles for halt to get to EX1

10 Question 4: Pipeline Performance (6 points) V2 Consider a normal 5-stage LC2K pipeline as discussed in class with the following features: ● Using detect-and-forward to handle data hazards. ● Using speculate-and-squash to handle control hazards and always predict "Not Taken". ● Branches are resolved in the MEM stage. ● Data memory access (and the critical timing path in the MEM stage) is 10 ns, while the critical path in every other stage is 6 ns Assume a benchmark with the following characteristics will be run on this pipeline: ● add/nor: 50% ● beq: 25% ● lw: 15% ● sw: 10% ● 30% of all branches are Taken ● 15% of lw instructions are immediately followed by a dependent instruction. ● 10% of lw instructions (disjoint from the previous percentage) are followed by a dependent instruction, but have a single non-dependent instruction between the lw and the dependent instruction. What is the CPI of this pipeline when running this benchmark? 1 + 0.25 * 0.3 * 3 (beq) + 0.15 * 0.15 * 1 (lw) = 1.2475 CPI Now, the MEM stage is split into two stages. It reduces the cycle time by splitting the data memory access latency equally between the MEM stages. Branches are resolved in the first MEM stage. What is the new CPI? 1 + 0.25 * 0.3 * 3 (beq) + 0.15 * 0.15 * 2 (lw) + 0.10 * 0.15 * 1 (lw) = 1.285 CPI Assuming 10 billion instructions execute, what is the total execution time for both the original (subquestion 1 above) and modified (subquestion 2 above) pipeline? Show your work for credit. Old execution time: 1.2475 * 10 billion * 10 ns = 12.925 * 10 9 * 10 -8 = 124.75 s New execution time: 1.285 * 10 billion * 6 ns = 12.85 * 10 9 * 6 * 10 -9 = 77.1 s Question 4: Pipeline Performance (6 points) V3 Consider a normal 5-stage LC2K pipeline as discussed in class with the following features: ● Using detect-and-forward to handle data hazards. ● Using speculate-and-squash to handle control hazards and always predict "Not Taken".

11 ● Branches are resolved in the MEM stage. ● Data memory access (and the critical timing path in the MEM stage) is 10 ns, while the critical path in every other stage is 6 ns Assume a benchmark with the following characteristics will be run on this pipeline: ● add/nor: 40% ● beq: 30% ● lw: 20% ● sw: 10% ● 30% of all branches are Taken ● 20% of lw instructions are immediately followed by a dependent instruction. ● 10% of lw instructions (disjoint from the previous percentage) are followed by a dependent instruction, but have a single non-dependent instruction between the lw and the dependent instruction. What is the CPI of this pipeline when running this benchmark? 1 + 0.3 * 0.3 * 3 (beq) + 0.20 * 0.20 * 1 (lw) = 1.31 CPI Now, the MEM stage is split into two stages. It reduces the cycle time by splitting the data memory access latency equally between the MEM stages. Branches are resolved in the first MEM stage. What is the new CPI? 1 + 0.3 * 0.3 * 3 (beq) + 0.20 * 0.20 * 2 (lw) + 0.10 * 0.20 * 1 (lw) = 1.37 CPI Assuming 10 billion instructions execute, what is the total execution time for both the original (subquestion 1 above) and modified (subquestion 2 above) pipeline? Show your work for credit. Old execution time: 1.31 * 10 million * 10 ns = 0.131 s New execution time: 1.37 * 10 million * 6 ns = 0.0822 s Question 4: Pipeline Performance (6 points) V4 Consider a normal 5-stage LC2K pipeline as discussed in class with the following features: ● Using detect-and-forward to handle data hazards. ● Using speculate-and-squash to handle control hazards and always predict "Not Taken". ● Branches are resolved in the MEM stage. ● Data memory access (and the critical timing path in the MEM stage) is 15 ns, while the critical path in every other stage is 12 ns Assume a benchmark with the following characteristics will be run on this pipeline: ● add/nor: 50% ● sw: 5% ● lw: 30% ● beq: 15% ● 40% of all branches are Not Taken ● 20% of lw instructions are immediately followed by a dependent instruction. ● 10% of lw instructions (disjoint from the previous percentage) are followed by a dependent instruction, but have a single non-dependent instruction between the lw and the dependent instruction.

13 Now, the MEM stage is split into two stages. It reduces the cycle time by splitting the data memory access latency equally between the MEM stages. Branches are resolved in the first MEM stage. What is the new CPI? CPI = 1 + 0.15 * 0.3 * 3 + 0.2 * 0.2 * 2 + 0.2 * 0.1 * 1 = 1.235 Assuming 10 billion instructions execute, what is the total execution time for both the original (subquestion 1 above) and modified (subquestion 2 above) pipeline? Show your work for credit. old exec time = 1.175 * 10^-8 * 10^10 = 117.5s new exec time = 1.235 * 6 * 10^-9 * 10^10 = 74.1s Question 5: Reverse Engineering the Cache (14 points) Assume the following: ● 8-bit byte-addressable ISA ● Cache size: <= 32B (not including overhead). ● Associativity: Fully-associative cache ● Cache block size and number of sets are both powers of two. ● Cache is initially empty. Given the following cache outcomes (hit/miss), determine the cache block size and number of cache blocks by answering the following questions. Access # Address Tag Cache Hit/ Miss 1 0x80 M 2 0xB4 M 3 0x81 H 4 0xAF M 5 0xAC H 6 0xB3 M 7 0x81 M

14 8 0x87 H 9 0x75 M 10 0x79 M 5.1) Cache block size is greater than or equal to (>=) N Bytes. Determine maximum value for N and enter only a number for N here: 8B - maximum referenced the largest lower bound possible (ie 8 is a larger lower bound than 2) partial credit was awarded when applicable due to confusion in wording Your choice of (>=) cache block size above is known because of which access numbers from the table (choose exactly two)? access # 7 & 8 Cache block size is less than (<) N Bytes. Determine minimum value for N and enter only a number for N here: 16 B - minimum referenced the smallest upper bound possible (ie 32 is a larger upper bound than 16) partial credit was awarded when applicable due to confusion in wording Your choice of (<) cache block size above is known because of which access numbers from the table (choose exactly two)? access 9 & 10 Therefore, cache block size is N Bytes (enter only a number for N here): 8B 5.2) Number of cache blocks is greater than (>=) N # of blocks (enter only a number for N here): question was intended to match wording for 5.1 and should have said greater than or equal to 2 blocks >= ● 1 was also accepted due to typo Your choice of (>=) number of cache blocks above is known because of which access numbers from the table? Choose exactly two accesses with the same tag: access # 1 & 3

16 Question 6: 3 C’s (2 Points) Consider a scenario where we increase the cache block size in a set-associative cache. Cache size and associativity is kept unchanged. Choose the answer for each of the following 4 sub-questions. 6.1) Number of sets: ❏ increases ❏ decreases ❏ remains the same 6.2) Number of cache blocks: ❏ increases ❏ decreases ❏ remains the same 6.3) Compulsory misses: ❏ increases ❏ decreases ❏ remains the same 6.4) Exploits spatial locality: ❏ better ❏ worse ❏ about the same Question 7: 3 C’s Part II (6 Points) Consider a byte-addressable architecture with the following cache: Cache size: 64 bytes Cache block size: 16 bytes Associativity: 2-way set-associative Assume that the cache is initially empty, and uses LRU replacement policy. Lower way is chosen when the set is empty. Answer the following questions for the list of memory references show in this table. (Empty columns are just workspace). Reference Tag Set Index Hit/Miss Type (if miss) Tag of evicted

17 block (if applicable) 0x0DD5 0x6E 0x1 miss compulsory - 0x1F07 0xF8 0x0 miss compulsory - 0x02AE 0x15 0x0 miss compulsory - 0x0509 0x28 0x0 miss compulsory 0xF8 0x2EDF 0x176 0x1 miss compulsory - 0x1F0F 0xF8 0x0 miss conflict 0x15 0x1F01 0xF8 0x0 hit - - 0x48D7 0x246 0x1 miss compulsory 0x6E 0x0DDA 0x6E 0x1 miss capacity 0x176 0x0380 0x1C 0x0 miss compulsory 0x28 7.1) List all the memory references that incur conflict misses in the cache. State each memory reference in the following format: ROW, address (0xZZZZ), tag (0xZZZ), set-index (0xZ), tag-of-replaced-block-if-any (0xZZZ) Each letter "Z" above stands for one hexadecimal digit. (e.g.,: ROW-X, 0x1234, 0x120, 0x1, 0x000) ROW-F, 0x1F0F, 0xF8, 0x0, 0x15 7.2) List all the memory references that incur capacity misses in the cache. State each memory reference in the following format: ROW, address (0xZZZZ), tag (0xZZZ), set-index (0xZ), tag-of-replaced-block-if-any (0xZZZ) Each letter "Z" above stands for one hexadecimal digit. (e.g.,: ROW-X, 0x1234, 0x120, 0x1, 0x000) ROW-I, 0x0DDA, 0x6E, 0x1, 0x176 7.3) At the end of simulating the above address sequence, specify the final state of the

19 Size of each 2nd level page table 2^ N Bytes (enter only the exponent number N here): 2^12 Bytes Size of 1st level page table index # bits (enter only the number here): 13 Bits Size of 1st level page table 2^ N Bytes (enter only the exponent number N here): 32 KB In the worst case, how much memory would this 3-level page table occupy? State your answer in the form 2^1 + 2^2 + … + 2^n bytes. 2 15 + 2 25 + 2 38 Bytes For the same page size, if this system used a single-level page table instead of a three- level page table, how much memory would it occupy in the worst case? State your answer in the form 2^1 + 2^2 + … + 2^n bytes. 2 38 Bytes Question 9: Hierarchical Page Tables (6.5 Points) Assume 16-bit ISA that uses a 3-level page table. Each virtual memory address is split into following fields: 1st level index size: 4 bits 2nd level index size: 6 bits 3rd level index size: 4 bits Physical page offset size: 2 bits Consider the following virtual addresses accessed in the order given below. Determine the 1st, 2nd and 3rd level indices for each access. Virtual Address 1st level index 2nd level index 3rd level index 0xA7E4 1010 011111 1001 0xB09B 1011 000010 0110 0xA78F 1010 011110 0011 0xC78F 1100 011110 0011 0xB098 1011 000010 0110 What goes in the three empty boxes for Row A, Virtual Address 0xA7E4? 1010 011111 1001

20 What goes in the three empty boxes for Row B, Virtual Address 0xB09B? 1011 000010 0110 What goes in the three empty boxes for Row C, Virtual Address 0xA78F? 1010 011110 0011 What goes in the three empty boxes for Row D, Virtual Address 0xC78F? 1100 011110 0011 What goes in the three empty boxes for Row E, Virtual Address 0xB098? 1011 000010 0110 How many first-level page tables will have been allocated after these 5 memory accesses? (enter only the number here) 1 How many second-level page tables will have been allocated after these 5 memory accesses? (enter only the number here) 3 How many third-level page tables will have been allocated after these 5 memory accesses? (enter only the number here) 4 Question 10: Virtual Memory (11 Points) Assume 16-bit ISA and the following system configuration. Cache: Physically addressed 2-way set associative Block size: 4 bytes Cache size: 16 bytes Latency for each memory component: