CSE_142_WI24_HW3

3. Cache Accesses (6 points - Correctness ): Complete the following table for each of the below cache configurations: (a) Cache size - 512 byte, 2-way set associative cache with 64-byte block size. (b) Cache size - 512 byte, fully associative cache with 64-byte block size. For each access fill the last column with the type of cache miss if it is a miss (Just write hit if it’s a cache hit). Use Least Recently Used (LRU) as the replacement policy. Show tag, index and offset bits calculation in the box below to get full credits. (You may use the empty space on the right side of the tables to keep track of the cache contents.) Cache (a) Cache (b) block offset Index Tag Sr. No. Address (in binary) Cache (a) (Type of Cache Miss) 1 0010 0110 0000 2 1101 1000 0100 3 0000 0110 0110 4 0101 1110 1010 5 1110 0100 1110 6 1010 0010 0000 7 0010 0110 0001 8 1011 1010 0011 9 1101 1000 1100 10 1000 1100 1100 11 1111 1010 0000 12 1011 1000 1011 13 0100 0000 1110 14 0111 1110 0010 15 0101 1111 1010 16 0111 1111 0011 17 1010 0000 0001 18 0010 0110 0001 19 1110 0110 0010 20 0100 0001 1000 21 1111 1010 1110 22 1011 1001 1011 23 1001 0011 1111 24 0101 1110 0010

6. TLB (6 points - Correctness ): Your TLB is 2-way set associative and holds 8 translations. It has the following entries. • Virtual memory address consist of 32 bits with a 12 bit page offset. • The virtual page number tag in the TLB excludes the 2 bit index and therefore is 18 bits. • The 18 bit of Virtual Page # Tag is shown in the TLB table below in the form: top 16 bits in hex (0xXXXX), bottom 2 bits (bXX) in binary. • The physical page number consists of 28 bits. Index Virtual Page # Tag Physical Page # Tag Virtual Page # Tag Physical Page # Tag 0 0x73C7, b10 0x1234567 0x5CDD, b01 0x7642861 1 0x6200, b00 0x345df44 0x3EEE, b10 0x2345647 2 0xCCD3, b01 0xDBB234D 0x1265, b10 0x234BDCE 3 0xF13F, b01 0xAB568BC 0x8DF1, b11 0x0187109 (a) Fill out the rightmost column of the memory access table below to denote whether the memory access was a hit or a miss in the TLB. The cache uses an LRU replacement policy, and you may assume that to start with, the right entry is the least recently used. You can use the below empty table to keep track of the entries in TLB while processing the memory accesses. Index Virtual Page # Tag Physical Page # Tag Virtual Page # Tag Physical Page # Tag 0 1 2 3 Virtual Mem Access Result (Physical Mem Address) Hit/Miss 0x73C78000 0x1234567000 0x62001077 0x345DF44077 0x8703C12E 0x764286712E 0x5CDD4AD2 0x7642861AD2 0x339541D0 0xDB32D781D0 0xBEEDD020 0x3091834020 0xA667B9DC 0x23456479DC 0xCCD35293 0xDBD234D293 (b) What are the contents of the TLB after processing the page accesses from (a)? Index Virtual Page # Tag Physical Page # Tag Virtual Page # Tag Physical Page # Tag 0 1 2 3