NAND2TETRIS HARDWARE SIMULATOR (HARDWARE DESCRIPTION LANGUAGE (HDL)) ,USING SKELETON PROGRAM PROVIDED AND USING PREDIFINED GATES ATTACHED.CHIP HiLoMux{IN in[8], sel;OUT out[4];PARTS:} Implement HiLoMux - This has one 8-bit input bus, in, and one 4-bit output bus, out. Alsopresent is a sel input, which is used to select what appears on out. Ifsel is false, then out should contain the lower 4-bits of in (i.e. in[0],in[1], in[2], in[3]). If sel is true, then out should contain theupper 4-bits of in (i.e. in[4] mapped to out[0], in[5], mapped toout[1], etc.). Not 4And4Or4Xor4Add4CRegister8This has one input bus, in, and one output bus, out. Each bit of the output isthe inverse (i.e. not) of the corresponding input bit.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of logically anding together the corresponding input bits in aand b.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of logically oring together the corresponding input bits in aand b.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of logically Xoring together the corresponding input bits in aand b.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of adding together the corresponding input bits in a and b,while making sure that any carry is propagated to the next bit.Add4 also has an additional carryIn input, which is used to feed carry into firstaddition, and a carryOut output which carries the carry out of the final addition.This gate has one 8-bit input bus, in, and one output bus, out, and is designedto store a single byte (8-bits) of information. As with pre-supplied Bit, a furtherinput load controls whether the output should be updated to reflect the newinput value (when true), or should preserve the output. Mux4Mux8This has two input buses, a and b and one output bus, out. Alsopresent is a sel input, which is used to select whether input a or b ispassed to out. If sel is false, input a should be selected, otherwiseinput b should be selected.This is an 8-bit version of Mux4. It has two input buses, a and b and oneoutput bus, out. Also present is a sel input, which is used to selectwhether input a or b is passed to out. If sel is false, input a should beselected, otherwise input b should be selected.Mux4Way8 This is essentially the same a the Mux8 except it can select betweenfour different inputs (a, b, c, and d) and so sel is two bits wide -hence, 4Way...Mux8Way8 This is essentially the same as the Mux4way8 defined above, howeverthis time there are eight inputs and sel is three bits wide. You shouldadapt your earlier implementation to reflect this change.

Question

NAND2TETRIS HARDWARE SIMULATOR (HARDWARE DESCRIPTION LANGUAGE (HDL)) ,USING SKELETON PROGRAM PROVIDED AND USING PREDIFINED GATES ATTACHED.CHIP HiLoMux{IN in[8], sel;OUT out[4];PARTS:}  Implement HiLoMux - This has one 8-bit input bus, in, and one 4-bit output bus, out. Alsopresent is a sel input, which is used to select what appears on out. Ifsel is false, then out should contain the lower 4-bits of in (i.e. in[0],in[1], in[2], in[3]). If sel is true, then out should contain theupper 4-bits of in (i.e. in[4] mapped to out[0], in[5], mapped toout[1], etc.). Not 4And4Or4Xor4Add4CRegister8This has one input bus, in, and one output bus, out. Each bit of the output isthe inverse (i.e. not) of the corresponding input bit.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of logically anding together the corresponding input bits in aand b.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of logically oring together the corresponding input bits in aand b.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of logically Xoring together the corresponding input bits in aand b.This has two input buses, a and b, and one output bus, out. Each bit of theoutput is the result of adding together the corresponding input bits in a and b,while making sure that any carry is propagated to the next bit.Add4 also has an additional carryIn input, which is used to feed carry into firstaddition, and a carryOut output which carries the carry out of the final addition.This gate has one 8-bit input bus, in, and one output bus, out, and is designedto store a single byte (8-bits) of information. As with pre-supplied Bit, a furtherinput load controls whether the output should be updated to reflect the newinput value (when true), or should preserve the output. Mux4Mux8This has two input buses, a and b and one output bus, out. Alsopresent is a sel input, which is used to select whether input a or b ispassed to out. If sel is false, input a should be selected, otherwiseinput b should be selected.This is an 8-bit version of Mux4. It has two input buses, a and b and oneoutput bus, out. Also present is a sel input, which is used to selectwhether input a or b is passed to out. If sel is false, input a should beselected, otherwise input b should be selected.Mux4Way8 This is essentially the same a the Mux8 except it can select betweenfour different inputs (a, b, c, and d) and so sel is two bits wide -hence, 4Way...Mux8Way8 This is essentially the same as the Mux4way8 defined above, howeverthis time there are eight inputs and sel is three bits wide. You shouldadapt your earlier implementation to reflect this change.

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In the first part of the book/course, we build the hardware platform of a simple yet…