For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag Index Offset 31–10 9–6 5–0 a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation over the data storage bits?

For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag Index Offset 31–10 9–6 5–0 a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation over the data storage bits?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 2VE

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