When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off . In the following three problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 450ps, 90ps, 25ps, 120ps, 200ps, 300ps, and 100ps, respectively, and costs of 900, 30, 10, 100, 200, 1500, and 500, respectively. Consider the addition of a multiplier to the ALU. This addition will add 200ps to the latency of
When processor designers consider a possible improvement to the processor datapath, the decision
usually depends on the cost/performance trade-off . In the following three problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 450ps, 90ps, 25ps, 120ps, 200ps, 300ps, and 100ps, respectively, and costs of 900, 30, 10, 100, 200, 1500, and 500, respectively. Consider the addition of a multiplier to the ALU. This addition will add 200ps to the latency of the ALU and will add a cost of 400 to the ALU. The result will be 7.5% fewer instructions executed since we will no longer need to emulate the MUL instruction.
1. What is the clock cycle time with and without this improvement?
2. What is the speedup achieved by adding this improvement?
3. Compare the cost/performance ratio with and without this improvement.
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