Try a 8051 microcontroller assembly code for the robotic gripper below that can perform the 3 criteria: - Move 90 degree -Move up and down -Grip an object 21
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- Q1 a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.) Part DigClock Part List: OFFTIME = .5uS DSTM1 ONTIME = .5us DELAY = STARTVAL = 0 OPPVAL = 1 DisClock FileStm1 FieStm16 CLK FileStim2 FileStim32 FileStim4 FileStime Libraries Design Cache EVAL 1. SOURCEplease meet the following requiremtents using the LC3 simulatorTask: DL34. In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output which is false only if all its inputs are true; thus, its output is complement to that of an AND gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is LOw (0), a HIGH (1) output results. A NAND gate is made using transistors and junction diodes. Minimum number of NAND gates required to implement the following binary equation (A'+B') (C+D)?
- Design and implement sequential digital circuit, with following specifications: It has one input X, two outputs Y1 and YO. Whenever an active HIGH is observed at input X at the active clock edge, circuit initiates a sequence and generates output waveforms given in figure below. (After the sequence is completed, it walts for input to be HIGH again) a) Use AND, OR, NOT gates and D type edge triggered flip-flops. Hint: Describe the circuit model Draw the State Diagram Find the State Table Make State Assignment with increasing numbers. (i.e. 0,1,2,3.) Write State and Output equations Draw the Circuit. : b) Use 74HC00, 74HC74 Integrated circuits for the implementation. c) Use 74HCO0, 74HC138 Integrated circuits for the implementation. re-start or intation of restart or ntiation of restart or sequence initiotion of new sequence ends here new sequence rewsequence 000 0 YO 000 000 0 0o0 0 Y1 ck nnn nn. no waiting male lorg watine typical esample eampieTrue or False: In Verilog hardware description language AND, OR, and an XOR gate primitives need multiple scalar inputs and produce a single scalar output.what are the issues of the d latch
- 1- A combinational circuit is defined by the following three functions: F1= XY + XYZ F2= XY + XYZ F3- XỸZ + 7Z Design the circuit with a decoder and external gates.HW: (a) Design a CMOS logic circuit that implements the logic function. f(A,B,C) = A + BC (b) Find the width-to-length ratios of the transistors in the CMOS logic circuit designed in (a). Symmetrical switching times are desired and the switching times should correspond to the basic CMOS inverter. 2403. Design an appropriate combinational circuit that implements a digital system with the following output functions an AC remote: ON, OFF, MODE, SHIFT, FAN, SMART, SWING, ECO using a decoder.