Question 2 (8) i) Processor having Clock cycle of 0.25ns will have clock rate of a) 2GHZ b) 3GHZ c) 4GHZ d) 8GHZ ii) If computer A executes a program in 10 seconds and computer B runs the same program in 15 seconds, what is the relative performance of computer A compared to computer B? a) 1.4 b) 1.5 c) 0.67 d) 1 iii) architecture implies, arithmetic and logic operations can only take place between CPU registers. iv) Using the following instruction format, a total of registers can be addressed. 8 7 10 OP code Source Dest Other info

Question 2 (8) i) Processor having Clock cycle of 0.25ns will have clock rate of a) 2GHZ b) 3GHZ c) 4GHZ d) 8GHZ ii) If computer A executes a program in 10 seconds and computer B runs the same program in 15 seconds, what is the relative performance of computer A compared to computer B? a) 1.4 b) 1.5 c) 0.67 d) 1 iii) architecture implies, arithmetic and logic operations can only take place between CPU registers. iv) Using the following instruction format, a total of registers can be addressed. 8 7 10 OP code Source Dest Other info

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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1. Suppose you are developing a processor with an execution time of 960 ns, CPIof 1.61, and clock rate of 3 GHz. If the execution time is reduced by an additional 20%without affecting to the CPI and with a clock rate of 4 GHz, determine the number ofinstructions. 2. Determine the clock rate if the CPI is increased by 20% and the CPU time by15% while the number of instructions is unchanged
Q5/ design an interfacing circuit for the memory to meet the following specification: 1- Microprocessor have 16 address line 2- 74LS 138 :3 to 8 decoder 3- 2732 (4 K x 8) :EPROM -address range should begin at 0000 H and additional 4K memory space should be available for future expansion 4- 6116 (2Kx 8): CMOS R/W memory And then identify the memory map
Q2. (a) Figure 2 shows the pinout diagram (and their functional description) of the 2114 Static RAM memory IC. Using a neat sketch show how such IC may be interfaced with an M68000 microprocessor to realise a system that needs 1K x 16 bits of RAM. [Note: 2114 is a 4-bit memory IC. You will need multiple ICs to make up the 16-bit data bus of the M68000 processor.] A6 1 A5 2 A4 3 A3 4 AO 5 A1 6 A2 7 CS 8 GND 9 18 Vcc 17 A7 16 A8 15 A9 14 I/O 1 13 1/0 2 12 1/0 3 11 1/0 4 10 WE ROM1 ROM2 ROM3 RAM Ao-Ag WE CS Figure 2 1/01-1/04 Vcc GND Truth Table CS H L L WE X L H 00 0000-00 1FFF 00 2000 - 00 3FFF 00 400000 7FFF 04 0000 - OF FFFF. Pin Names Address Inputs Write Enable Chip Select Data Input/Output Power (+5V) Ground (b) Determine the logic expressions to implement an address decoding circuit to realize the memory address map shown below. Use partial address decoding technique in your design. You only need to show the truth table and the resulting logic equations. No need to draw the…
[2] A digital computer has a common bus system for 8 registers (R1... R8) of 16 bits each. thare in h mlsinleva2 (d) Construct the common bus system with multiplexers; show their inputs and their selection variables (SO, S1). (e) Draw a diagram of a bus system, using three-state buffers and a decoder.
ote: sclon Sundwame OT J01n0 Consider the two computers A and B with the clock cycle times 100 ps and 150 ps respectively for some program. The number of cycles per instruction (CPI) for A rnd B are 2.0 and 1.0 respectively for the same program. Which computer is faster and how much? a) A is 1.33 times faster than B b) Bis 1.22 times faste than A c) Ais 1.23 times faster than B d) Bis 1.33 times faster than A Answer Submit
(a) Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. a. Which processor has the highest performance expressed in instructions per second? b. If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions. c. We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?
Suppose you are developing a processor with an execution time of 960 ns, CPI of 1.61, and clock rate of 3 GHz. If the execution time is reduced by an additional 20% without affecting to the CPI and with a clock rate of 4 GHz, determine the number of instructions.
Assume in a computer A, the execution time equals 960 ns, CPI of 1.61, and clock rate of3GHz. If the execution time is reduced by additional 10% without affecting the CPI and with aclock rate of 4 GHz, determine the number of instructions.
Consider a Instruction pipeline having 5 phases with duration 20, 40, 60, 80 and 80 ns. Given latch delay is 5 ns. Calculate the following parameters: ) Pipeline cycle time (i) Non-pipeline execution time Cii) Speed up ratio (iv) Pipeline time for 2000 tasks (V) Sequential time for 2000 tasks (vi) Throughput Also, draw the block diagram showing the pipelined architecture. (Note : Solve the question in paper, scan and upload along with the other Part B and C answers)
Assume for arithmetic, load/store, and branch instructions, a processor has CPIs of 1, 12, and 5, respectively. Also assume that on a single processor a program requires the execution of 2.56E9 arithmetic instructions, 1.28E9 load/store instructions, and 256 million branch instructions. Assume that each processor has a 2 GHz clock frequency. Assume that, as the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions per processor is divided by 0.7 x p (where p is the number of processors) but the number of branch instructions per processor remains the same. Find the total execution time for this program on 1, 2, 4, and 8 processors, and show the relative speedup of the 2, 4, and 8 processor result relative to the single processor result. If the CPI of the arithmetic instructions was doubled, what would the impact be on the execution time of the program on 1, 2, 4, or 8 processors? To what should the CPI of load/store instructions be…
3. A non-pipelined processor has a clock rate of 2.5GHZand an average CPI of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to2GHz. 3.1 What is the speedup achieved for a typical program? Assume that it consists of 100 instructions. The speedup is the ratio between the two processors in terms of the time required to execute the program. 3.2 What is the MIPS rate for each processor? In case of the pipelined processor, ignore the initial filling up.
a)How many instructions are executed per second by a machine which has a clock frequency of 40MHz and takes 10 cycles to execute an instruction? b)If computer A runs a program in 20 seconds and computer B runs the same program in 35 seconds, how much faster is A than B? c)Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 4 GHz clock rate and a CPI of 1.5. P2 has a 3 GHz clock rate and a CPI of 1.0. P3 has a 1.3 GHz clock rate and has a CPI of 2.2. (i) Which processor has the highest performance expressed in instructions per second? (ii) If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions.