QUESTION 1: If a CPU has 32 address lines for address bus and 64 bits' data buses. Answer the following questions: a) Show the design of fully associative L1 cache with 212 rows. b) Show the design of direct mapped cache with 216 row rows.
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Q: QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable…
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes. a. What is the number of sets in the cache? b. What is the size (in bits) of the tag field per cache block? c. What is the number and size of comparators required for tag matching? d. How many address bits are required to find the byte offset within a cache block? e. What is the total amount of extra memory (in bytes) required for the tag bits?For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0
- If a CPU has 32 address lines for address bus and 64 bits' data buses. Answer the following questions: a) .Show the design of fully associative L1 cache with 212 rows. b) Show the design of direct mapped cache with 216 rows.Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes. How many words of data are included in one cache line?
- CO. A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index ticlds respectively in the addresses generated by the processor?A microprocessor with 32-bit address bus has an on-chip 16-KByte four-way set-associative cache memory, the line size is 4 bytes. Draw a block diagram of this cache showing its Organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?Design a cache with cache size of 128K bytes, block (line) size of 8 words, and word size of 4 bytes. Consider a computer with 64-bit physical address. The cache is addressed by physical address. a. Determine the tag array size (in bytes) for three cache implementations (direct-mapped, 16-way, set-associative, and fully associative). b. Using the tag array sizes computed in (a), compare the percentage overhead of different cache designs. In other words, compute the percentage of the tag array compared to the original cache design (128K), and identify the best, moderate and worst cache implementations in terms of tag area overhead. c. Why would anyone use the implementation you identified in (b) with worst area (tag array) overhead? In other words, identify a scenario when a designer will use the cache implementation that you identified in (b) with worst area overhead.
- Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag and offset fields?For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes. How many entries does the cache have?A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressing is used.Q.) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.