Q2 Design a switching network that select one of five of 6-input data words with three control input ABC where the data that appear at the output (Z) depends on the value of control input as shown below : ABC Output (Z) 000 N 1 001 M 2 100 X 3 101 Y u 111 L 5
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- Write an 8051 asm program to design a voltage level indicator system using potentiometer and LEDS. The system must display the different level of the voltage with the help of 5 LEDS as per following conditions. a) If the voltage is between 0 to 1V glow LED1 b) If the voltage is between 1 to 2V glow LED1 and LED2 c) If the voltage is between 2 to 3V glow LED1 to LED3 d) If the voltage is between 3 to 4V glow LED1 to LED4 e) If the voltage is between 4 to 5V glow LED1 to LED55- Write a C code that generates a 100 cycles only of waveform at variable frequency where the output frequency is given by: foutput = 5 + n Hz, where n is the Cycle Number n= 0,1, 2..... .99. The output is available from RB10. Given that Fcy = 50 MHz.Computer Science A circuit for two output ports (A&C) of the AVR ATmega16 microcontroller each connected to 8 LEDs. Write a program to control the LEDs in a sequence shown by stepping to lit on the LED sequentially as in the figure by toggling the LED at the same time for both ports (500mS) ending at the last state of the figure and looping back inversely to the start. This s done for 3 times back and forth.
- A DFA is defines as (Q, S, 6, q0, F) where Q (q0, q1, q2, q3, q4, q5), S= (0, 1), F= (q3, 94), and the transilion function & is defined as in table below: q0 (start) q1 q2 q1 q1 93 q2 94 92 q3 (accepting state) q5 q5 94 (accepting state) q5 q5 q5 q5 Show/prove that this DFA is minimal or otherwise?Q19/ a combinational circuit has four inputs (A, B, C, D), which represent a binary- coded- decimal digit. The circuit has two groups of four outputs S, T, U, V, and W, X, Y, Z each group represents a BCD digit. The output digits represent a decimal number which is 1 more than four times the input number. For example if ABCD=0011, the output are 0001 0011. Assume that invalid BCD digits do not occur as inputs. a- Construct the truth table b- Write minterms and max terms for all output C- Find SOP and POS for all outputQ4// Design a combinational circuit with three inputs, A, B, and C, and three outputs,x, y, bläi 10 and z. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is two * less than the input
- Q1: Design a Moore FSM to detect if an input sequence is divisible by 5. Each cycle a new bit comes as input towards LSB (e.g. if the current sequence is '1011' and the input is '0', the new sequence is '10110'). The FSM outputs a logic 1 if the sequence is divisible by 5, otherwise it outputs a logic 0. The starting point for the state diagram and a description of what the state does is depicted below. And assume initially the system is in state S0. a) Draw the Moore state diagram for this FSM using a minimum number of states. b) Draw the excitation table for the states. Define the states in order; e.g. S0 = 000, S1 = 001 etc. c) Write the minimum SOP Expression for all the bits of the states and the output 'O'. I: 0 so All 0 S1 Remainder 1QI: A: Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four operations in conjunction with the input carry Cin. Draw the logic diagram for the first two stages. S Cin Operation 0 0 0 1 1 0 1 1 A - B A +B A Add A-19. A multiplexer is a switching circuit that produces as its single output one of a set of inputs based on the value of some additional inputs called the controls. Given that 0, 1, 2, and 3 in two-bit binary are 00, 01, 10, and 11, respectively, draw a 2-bit multiplexer using the three basic logic gates with inputs xo, x1, x2, and x3, and two control inputs co and c1. Setup the circuit so that x; is the single output, where i if the value of the 2-bit integer (cico)2. NOTE: This is not a Boolean product; instead it's the binary representation of an integer where c1 is the most significant bit and co is the least significant bit.
- r1'• r0' waitr1 waitro 1'• r0 r1• r0' r1 r1 grant1 g1<=1 granto g0<=1 The following entity describes the circuit above: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity arbiter2 is port ( clk : in std_logic ; reset : in std_logic ; r: in std_ logic_vector (1 downto 0) ; g: out std_ logic_vector (1 downto 0) end arbiter2 ; Assume the point of entry on reset is the state waitr1. Write the architecture VHDL for this FSM.4- Write a C code that generates 40 cycles only of waveform at 5 Hz. The output is available from RA2. Given that Fcy = 40 MHz.Question Completion Status: O 2,048 QUESTION5 The following logic circuit is B8 A8 B7 A7 |B6 |A6 B5 A5 B4 A4 B3 A3 B2 A2 | B1 A1 FA8 2FA7 C6 FA6 *C5 C4 FA4 C3 FA1 Cin FA5 FA3 C2 FA2 C1 S8 S7 S6 S5 S4 S3 C8 S2 S1 CElprocus.com O 8- bit - Full adder O 8- bit - half adder O 8- bit - Decoder 08-bit- Multiplexer QUESTION 6 A Write the Boolean equation directly from the following circuit. (2 marks ) B Create the truth table for the circuit above (3 Marks)