"Figure 5.7" in the statement is show below. This picture is from Computer Architecture: A Quantitive Approach Write-back blockWrite missfor blockCPU write hitCPU read hitInvalidPlace write miss on busCPU writeWrite miss for this blockInvalidate for this blockExclusive(read/write)CPU readPlace read miss on busCPU read missWrite-back data; place read miss on busCPU writeRead miss for block Write-back blockPlace invalidate on busCPU write missCPU write missPlace write miss on busWrite-back dataPlace write miss on busCPUreadhitShared(read only)CPUreadmissPlace readmiss on busFigure 5.7 Cache coherence state diagram with the state transitions induced by thelocal processor shown in black and by the bus activities shown in gray. As inFigure 5.6, the activities on a transition are shown in bold. Problem 2Complete the following table, filling in the state transitions specificallyfor Processor 1, block Assume a cache with a write-back policy (cache can hold only oneblock at a time) which is initially empty. Include the new state of block A in Processor 1 onlyafter each event, and note any external actions taken by Processor 1. Assume that these accessesoccur in order, and that no other traffic occurs at the same time. Here, ESI refers to the standardsnoopy protocol in Figure 5.7 (page 361), whereas MESI is the modified snoopy protocol in thelecture slide which uses an additional state. Please note that M (modified) state in MESI is infact similar to the E (exclusive) state in ESI, and E (exclusive) state in MESI is anadditional (read/only) state. To avoid this confusion, some literature uses the term MSI to referto ESI protocol.EventLocal Write ALocal Read BBus Read ABus Write ALocal Write ALocal Read ABus Read ALocal Write ALocal Write BLocal Read ALocal Write ALocal Write BESI forblock AEMESI forblock AMExternal actions for ESI and MESIBoth send invalidations

LOAD read B. In the cache, there is A because of previous instructions. Therefore, this is a…

Problem Complete the following table, filling in the state transitions specifically for Processor 1, block A. Assume a cache with a write-back policy (cache can hold only one block at a time) which is initially empty. Include the new state of block A in Processor 1 only after each event, and note any external actions taken by Processor 1. Assume that these accesses occur in order, and that no other traffic occurs at the same time. Here, ESI refers to the standard snoopy protocol in Figure 5.7 (page 361), whereas MESI is the modified snoopy protocol in the lecture slide which uses an additional state. Please note that M (modified) state in MESI is in fact similar to the E (exclusive) state in ESI, and E (exclusive) state in MESI is an additional (read/only) state. To avoid this confusion, some literature uses the term MSI to refer to ESI protocol.

Problem Complete the following table, filling in the state transitions specifically for Processor 1, block A. Assume a cache with a write-back policy (cache can hold only one block at a time) which is initially empty. Include the new state of block A in Processor 1 only after each event, and note any external actions taken by Processor 1. Assume that these accesses occur in order, and that no other traffic occurs at the same time. Here, ESI refers to the standard snoopy protocol in Figure 5.7 (page 361), whereas MESI is the modified snoopy protocol in the lecture slide which uses an additional state. Please note that M (modified) state in MESI is in fact similar to the E (exclusive) state in ESI, and E (exclusive) state in MESI is an additional (read/only) state. To avoid this confusion, some literature uses the term MSI to refer to ESI protocol.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
A two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.
Here is the question: A direct-mapped cache consists of 8 blocks. A byte-addressable main memory contains 4K blocks of eight bytes each. Access time for the cache is 20 ns and the time required to fill a cache slot from main memory is 300 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. b) Compute the hit ratio for a program that loops 3 times from address 0 to 75 (base 10) in memory. For b, another example has been provided in regards to a previous problem: A direct-mapped cache consists of eight blocks. Main memory contains 4K blocks of eight words each. Access time for the cache is 22 ns and the time required to fill a cache slot from main memory is 300ns (this time will allow us to determine the block is missing and bring it into cache). Assume a request is always started in parallel to both cache and to…
2-Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. a. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. 42, 180, 46, 185, 189, 3, 181, 43, 6, 189, 65, 190 b. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with four-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. c. For each of these references, identify the binary address, the tag, and the index given a two way associative cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty d. For each of these…
“Prefetching” is a technique that leverages predictable address patterns to speculatively bring in additional cache blocks when a particular cache block is accessed. One example of prefetching is a stream buff er that prefetches sequentially adjacent cache blocks into a separate buff er when a particular cache block is brought in. If the data is found in the prefetch buff er, it is considered as a hit and moved into the cache and the next cache block is prefetched. Assume a two-entry stream buff er and assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. What is the miss rate for the address stream above?Cache block size (B) can aff ect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes. 8: 4% 16: 3% 32: 2% 64: 1.5% 128: 1%…
Assume a direct-mapped cache that holds 4096 bytes, in which each block is 16 bytes. Assuming that an address is 32 bits and that cache is initially empty, complete the table that follows.(You should use hexadecimal numbers for all answers.) Which, if any, of the addresses will cause a collision (forcing the block that was just brought in to be overwritten) if they are accessed one right after the other?
Is there a way to find out which parts of a log entry a certain log processing function can read? The following code determines the typical number of cache misses per entry while using 64-byte cache blocks and no prefetching.
2. MESI Cache Coherence Protocol. In this question, we will explore MESI cache coherence protocols for a processor with four cores. You are given the initial cacheline coherence protocol state for variable x and the next sequence of requests for variable x (either store to x or load from x). This question only considers the state of the L1 cache. Fill in the blank cells that describe the cacheline coherence state after each request. No further explanation is required, but the work shown may be given partial credit. Request Type Cache Line State Core 1 Core 2 I I Request from Core # Initial Core 2 Core 3 Core 1 Core 1 Store Load Store Load Core 0 I Core 3 M
To what extent does the specified log processing function have access to each field of a log entry? The following code determines the typical number of cache misses per entry while using 64-byte cache blocks and no prefetching.
To what extent does the specified log processing function have access to each field of a log entry? The following code estimates the average number of cache misses per entry while using 64-byte cache blocks and no prefetching.
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses.3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
8. Assume a cache with a write-through policy, non-write allocate. Your cache has a miss rate of 4%. There is a 120 cycle miss penalty. Additionally, it takes an extra 30 cycles to do a write. Your program has a base CPI of 1, is 30% loads, and 10% stores. What will its CPI be?