Problem 4. Consider a memory system with a cache and main memory. It takes 10ns to access the cache, and 100ns to access the main memory. If the effective (memory) access time is 10% greater that the cache access time, what is the hit ration H?

Problem 4. Consider a memory system with a cache and main memory. It takes 10ns to access the cache, and 100ns to access the main memory. If the effective (memory) access time is 10% greater that the cache access time, what is the hit ration H?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Problem 4.
Consider a memory system with a cache and main memory. It takes 10ns to access the cache, and 100ns to access the main memory.
If the effective (memory) access time is 10% greater that the cache access time, what is the hit ration H?

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Question 2: Given that the main memory access time is 1200 ns and cache access time is 100 ns. The average memory access time is not to exceed 120 ns. What is the hit ratio for the cache must be at least?
Q2: Consider a non-overlapped memory system that has two levels of memories. The cache memory has an access time of 100 ns and the RAM memory has an access time of 1200 ns. If the effective access time is 50% greater than the cache access time. What is the hit ratio H?
a. We are given a system with 2 levels of cache, L1 and L2. The CPU directly interfaces to the L1 cache, which has a hit time of 1 ns and a hit rate of 0.4. On misses, the L1 accesses the L2 cache, which has an access time of 20 ns, and a hit rate of 0.8. If the L2 misses, it accesses the main memory, which has an access time of 100 ns. Determine the average memory access time, of the CPU to the memory hierarchy.b. A cache is inserted between the main memory, which is 32 MB, and the CPU. This cache can accomodate 64 blocks and each block can accomodate 128 words (2B per word). How many possible blocks can be stored in one cache block if it is a direct-mapped cache?
4. Practice Problem: • A computer has a cache, main memory, and a disk used for virtual Memory • An access to the cache takes 10 ns • An access to main memory takes 100 ns • An access to the disk takes 10,000 ns Suppose the cache hit ratio is 0.9 and the main memory hit ratio is 0.8. What is the effective access time (EAT) in ns required to access a referenced word on this system?
Consider we have two levels of cache, backed by a main memory (RAM). You are given with the following information about the access time for different level in the memory hierarchy L1 cache costs 1 cycle to access and has a miss rate of 8% L2 cache costs additional 5 cycles to access and has a miss rate of 4% RAM costs additional 40 cycles to access (and has a miss rate of 0%) What is the average memory access time (AMAT)?
Problem 4. There are two levels L1 and L2 of caches. L1 has hit rate 95%, and L2 has hit rate 80%. L1 has I cycle to access. L2 has 20 cycles to access. Memory has 400 cycles to access. Ignoring memory access clocks per instruction (CPI) has 1 cycle. Assume that 40% instruction has data access. Compute the CPI that includes memory access. You need to consider that there is a memory access to fetch each instruction.
Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs). (a) What is the overall memory access time given a cache hit rate of 95%? (b) What will the cache hit rate need to be if the overall memory access time in (a) is to be halved?
Answer the following questions. A. A computer system has a main memory access time as 60ns. you as a computer organization expert has been asked to reduce the memory access time to 20ns by adding a suitable cache. Assume that the miss probability is 10%. What should be the fastness of cache (in terms of access time) for this requirement? B. Consider the instruction ADD R1, X, which adds the contents of location X from the contents of register R1, and places the result in R1. Show the micro-operations used during fetch and execution phase of the instruction.
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
Consider a two-level memory system (i.e., cache and main memory). Assume the cache access time is 3 clock cycles, and the hit rate is 95%. What should be the main memory access time (penalty) to ensure the memory access efficiency stays at 0.90?
Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?
a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles.