Problem 1. A virtual memory has a page size of 1024 words, eight virtual pages, and four physical page frames. The page table is as follows: Virtual page 0 1 2 3 4 5 6 7 Page frame 3 1 not in main memory not in main memory 2 not in main memory 0 not in main memory a. Make a list of all virtual addresses that will cause page faults. b. What are the physical addresses for 0, 3728, 1023, 1024, 1025, 7800, and 4096?

Problem 1. A virtual memory has a page size of 1024 words, eight virtual pages, and four physical page frames. The page table is as follows: Virtual page 0 1 2 3 4 5 6 7 Page frame 3 1 not in main memory not in main memory 2 not in main memory 0 not in main memory a. Make a list of all virtual addresses that will cause page faults. b. What are the physical addresses for 0, 3728, 1023, 1024, 1025, 7800, and 4096?

Name: Can you explain the step ??? 1. / 3Homework 381% +Problem 1. A virtual
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Description: Can you explain the step ??? 1. / 3Homework 381% +Problem 1. A virtual memory has a page size of 1024 words, eight virtualpages, and four physical page frames. The page table is as follows:Virtual page01234567Page frame31not in main memorynot in main

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Below is a list of 32-bit memory address references, given as memory addresses. 12, 720, 172, 8, 764, 352, 760, 56, 724, 176, 744You would like to access a cache with the given memory addresses. The size of cache is 23 = 8-blocks. Your task is to: (1) find out the binary address, (2) fill out the tag and index for each memory address and (3) indicate whether the access is hit or miss in the following table:
A virtual memory has a page size of 2K(words). There are eight pagesand four blocks. The associative memory page table contains the followingentries:Page Block0 32 15 26 0Make a list of all virtual addresses (In decimal) that will cause a page fault if used by the CPU.
Suppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?
Suppose a computer using direct mapped cache has 2^32 bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. a) how many blocks of main memory are there? b) what is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields? c) to which cache block will the memory address 13A4498A map?
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?
Suppose a computer using direct mapped cache has 236 bytes of byte-addressable main memory and a cache size of 1024 bytes, and each cache block contains 64 bytes. ⦁ How many blocks of main memory are there? ⦁ What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields? ⦁ To which cache block will the memory address 0x13A4576B map?
Suppose a computer using fully associative cache has 4 GB of byte-addressable main memory and a cache of 256 blocks, where each block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0X1A1B1C1D map?
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
8.14. In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S t
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Suppose a computer using fully associative cache has 4G bytes of byte-addressable main memory and a cache of 512 blocks, where each cache block contains 128 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x018072 map?