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- IV) Convert Decimal to Hexadecimal (a) 974510 (b) 2976.5410 V) Convert from Binary to Hexadecimal (a) 10010110101012 (b) 111011101.010101012 VI) Convert from Hexadecimal to Binary (a) 7CAB516 (b) AF2.12B16- The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates. - Set up the circuits you designed with NAND and NOR gates and observe the outputs. Show the output values by drawing a table, applying all possibilities to the input values.Q#01: The schematic shown in figure below is for Divide_by_11, a frequency divider, that divides clk by 11 and asserts its output for one cycle. The unit consists of a chain toggle-type flip-flops with additional logic to form an output pulse every 11th pulse of clk. The asynchronous signal rst is active-low and drives Q to 1. Develop and verify a model of Divide_by_11. Vcc 20LSB Q2 03MSB clk clk clk clk clk rst rst rst rst wl w2 clk QB cik_by_11 rst rst
- - The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates.a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)Add the following BINARY NUMBERS 100010111.10111+ 101100001.11010
- What parity bit, P, should be added to the following data if the parity is EVEN? If the parity is ODD? a. 1111100 b. 1010110 c. 0001101Convert the 8-bit compressed code 00111010 to 12 bits PCM linear code.Problem_#08] The waveforms shown below are inputs to a 4-bit binary counter. The input signals represents the clock, count enable, and asynchronous clear. Develop the output waveform. CTEN CTEN - CTR DIV 16 CLK CLK C CLR - CLR CLR
- 1What will be the state of a MOD64 counter after 90 input pulses if the starting state=000000?A.100100B.011010C.010110D.011100 2.A MOD 32 counter is holding the count 101112. What will the count be after 31 clock pulses?A.10100B.10010C.10000D.10110If for 9bit ADC, VREF+=4V, VREF-=0 then 1.8V is binary encoded as: O a. 11100001 O b. 10011011 O. 11100110 O d. 10011011Assuming even parity, find the parity bit for each of the following data units. a. 1001010 b. 0001101 c. 1000000 d. 1110111