odify the following code to simulate a PEP/8 computer and instruction set for only the following instructions in the Image attached, to work in PEP/8 assembly language program : ORG $4000; start program ; start of program EQU MEMSIZE,$1000;size of memory   ;Createing a structure to emulate the registers STRUCT Registers A RESW 1 ; register A X RESW 1 ; register X PC RESW 1 ; Program counter SP RESW 1 ; Stack pointer ENDS   SECTION.BSS; declare variables

Systems Architecture
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Author:Stephen D. Burd
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Chapter3: Data Representation
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Modify the following code to simulate a PEP/8 computer and instruction set for only the following instructions in the Image attached, to work in PEP/8 assembly language program :

ORG $4000; start program ; start of program

EQU MEMSIZE,$1000;size of memory

 

;Createing a structure to emulate the registers

STRUCT Registers

A RESW 1 ; register A

X RESW 1 ; register X

PC RESW 1 ; Program counter

SP RESW 1 ; Stack pointer

ENDS

 

SECTION.BSS; declare variables

REGS Registers; registers

MEM RESW MEMSIZE; Memory array

ENDSEC

 

ORG $4000; start program

LDX #$FF ; Initialize X to highest memory address

STX REGS.SP; Set stack pointer to highest memory address

CLRA ; clear A

LDX #MEM; set X to point to the start of memory array

LDAB #10 ; load the value 10 to B

STAB 0,X ; Store 10 in first memory location

LDX #MEM+2 ; Set X to point to third memory location

LDAB #5 ; load 5 to B

STAB 0,X ; store 5 in the third memory location

LDX #MEM ; set X to point in the start of the array

LDAA 0,X ; Load the first number for memory to A

LDX #MEM+2 ; Set X to point to third memory location

ADDB 0,X ; Add the second number to B

STAA REGS.A ; store the result in A

HALT ; Halt

 

Here are some specifics for the modification.
1. Use an array to represent the memory.
 
2. Use variables or arrays for the PEP8 registers. I recommend putting it all into a
structure. I also recommend using an array of 16 bit values for A, X, PC, SP so
that you can use the r bit from the instructions to point directly to A or X. You do
NOT have to include the Status bits.

3. Use unions of structures to break up the registers and instructions into the correct
bits (for example, use a structure that can be unioned to break up the 8 bit
specifier into the following bit combos (4, 1, 3), (5, 3), (7, 1), (8). This will allow
you to instantly extract the instruction, register and addressing modes from each
instruction. Also use a union to break up the 16 bit operand into two 8 bit values.

4. Have the instructions be inputted either through the command line or better yet,
through a file, in the following format for each instruction, 6 Hexadecimal characters per instruction

5. After each instruction in the program is executed, output the PEP8 machine register values
Instruction
Specifier
0000 0000
0001 100r
0001 110r
0001 111r
0010 000r
0010 001r
0011 0aaa
0011 laaa
0100 laaa
0101 0aaa
0111 raaa
1000 raaa
1001 raaa
1010 raaa
1100 raaa
1101 raaa
1110 raaa
1111 raaa
Instruction
Stop execution
Bitwise invert r
Arithmetic shift left r
Arithmetic shift right r
Rotate left r
Rotate right r
Decimal input trap
Decimal output trap
Character input
Character output
Add to r
Subtract from r
Bitwise AND to r
Bitwise OR to r
Load r from memory
Load byte from memory
Store r to memory
Store byte r to memory
Addressing
Modes
ΝΑ
ΝΑ
ΝΑ
ΝΑ
ΝΑ
ΝΑ
d
d, i
d
d, i
d, i
d, i
d, i
d, i
d, i
d, i
d
d
Status Bits
NZ
NZVC
NZC
C
C
NZV
NZVC
NZVC
NZ
NZ
NZ
NZ
Transcribed Image Text:Instruction Specifier 0000 0000 0001 100r 0001 110r 0001 111r 0010 000r 0010 001r 0011 0aaa 0011 laaa 0100 laaa 0101 0aaa 0111 raaa 1000 raaa 1001 raaa 1010 raaa 1100 raaa 1101 raaa 1110 raaa 1111 raaa Instruction Stop execution Bitwise invert r Arithmetic shift left r Arithmetic shift right r Rotate left r Rotate right r Decimal input trap Decimal output trap Character input Character output Add to r Subtract from r Bitwise AND to r Bitwise OR to r Load r from memory Load byte from memory Store r to memory Store byte r to memory Addressing Modes ΝΑ ΝΑ ΝΑ ΝΑ ΝΑ ΝΑ d d, i d d, i d, i d, i d, i d, i d, i d, i d d Status Bits NZ NZVC NZC C C NZV NZVC NZVC NZ NZ NZ NZ
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