MODIFY THIS VERILOG CODE. THE OUTPUT OF THE QA,QB & QC (that will be seen on gtkwave) SHOULD BE: qa qb qc 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 1 module finals_nake(in, clk, qa, qb, qc); input in, clk; output qa, qb, qc; wire ja, jb, jc, ka, kb, kc; // Negated inputs wire in_n, clk_n; assign in_n = ~in; assign clk_n = ~clk; // JK equations based on provided equations assign ja = (qb & ~qc & ~in) | (qb & qc & in); assign ka = clk & clk; assign jb = (~qa & ~qc & ~in) | (~qa & qc & in); assign kb = qa | (~qc & ~in) | (qc & in); assign jc = (~qc & ~in) | (~qc & in); assign kc = clk & clk; //jka wire jka1, jka2, jka3, jka4; assign jka1 = ~(jka4 & ja); assign jka2 = ~(jka3 & ka); assign jka3 = ~(jka1 & jka4); assign jka4 = ~(jka2 & jka3); assign qa = jka3; //jkb wire jkb1, jkb2, jkb3, jkb4; assign jkb1 = ~(jkb4 & jb); assign jkb2 = ~(jkb3 & kb); assign jkb3 = ~(jkb1 & jkb4); assign jkb4 = ~(jkb2 & jkb3); assign qb = jkb3; //jkc wire jkc1, jkc2, jkc3, jkc4; assign jkc1 = ~(jkc4 & jc); assign jkc2 = ~(jkc3 & kc); assign jkc3 = ~(jkc1 & jkc4); assign jkc4 = ~(jkc2 & jkc3); assign qc = jkc3; endmodule module finals_nake_tb(); reg in, clk; wire qa, qb, qc; finals_nake finals_nake_ins(in, clk, qa, qb, qc); initial begin in = 0; clk = 0; #10 in = 0; clk = 1; #10 in = 0; clk = 0; #10 in = 0; clk = 1; #10 in = 0; clk = 0; #10 in = 0; clk = 1; #10 in = 0; clk = 0; #10 in = 0; clk = 1; #10 in = 0; clk = 0; #10 in = 0; clk = 1; #10 in = 0; clk = 0; #10 in = 1; clk = 1; #10 in = 1; clk = 0; #10 in = 1; clk = 1; #10 in = 1; clk = 0; #10 in = 1; clk = 1; #10 in = 1; clk = 0; #10 in = 1; clk = 1; #10 in = 1; clk = 0; #10 in = 1; clk = 1; #10 in = 1; clk = 0; #10 in = 1; clk = 1; #10 in = 0; clk = 0; end initial begin $dumpfile("finals_nake_ins.vcd"); $dumpvars(); $finish; end endmodule
MODIFY THIS VERILOG CODE. THE OUTPUT OF THE QA,QB & QC (that will be seen on gtkwave) SHOULD BE:
qa qb qc
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
0 0 1
1 0 1
1 0 1
0 0 1
module finals_nake(in, clk, qa, qb, qc);
input in, clk;
output qa, qb, qc;
wire ja, jb, jc, ka, kb, kc;
// Negated inputs
wire in_n, clk_n;
assign in_n = ~in;
assign clk_n = ~clk;
// JK equations based on provided equations
assign ja = (qb & ~qc & ~in) | (qb & qc & in);
assign ka = clk & clk;
assign jb = (~qa & ~qc & ~in) | (~qa & qc & in);
assign kb = qa | (~qc & ~in) | (qc & in);
assign jc = (~qc & ~in) | (~qc & in);
assign kc = clk & clk;
//jka
wire jka1, jka2, jka3, jka4;
assign jka1 = ~(jka4 & ja);
assign jka2 = ~(jka3 & ka);
assign jka3 = ~(jka1 & jka4);
assign jka4 = ~(jka2 & jka3);
assign qa = jka3;
//jkb
wire jkb1, jkb2, jkb3, jkb4;
assign jkb1 = ~(jkb4 & jb);
assign jkb2 = ~(jkb3 & kb);
assign jkb3 = ~(jkb1 & jkb4);
assign jkb4 = ~(jkb2 & jkb3);
assign qb = jkb3;
//jkc
wire jkc1, jkc2, jkc3, jkc4;
assign jkc1 = ~(jkc4 & jc);
assign jkc2 = ~(jkc3 & kc);
assign jkc3 = ~(jkc1 & jkc4);
assign jkc4 = ~(jkc2 & jkc3);
assign qc = jkc3;
endmodule
module finals_nake_tb();
reg in, clk;
wire qa, qb, qc;
finals_nake finals_nake_ins(in, clk, qa, qb, qc);
initial
begin
in = 0; clk = 0;
#10 in = 0; clk = 1;
#10 in = 0; clk = 0;
#10 in = 0; clk = 1;
#10 in = 0; clk = 0;
#10 in = 0; clk = 1;
#10 in = 0; clk = 0;
#10 in = 0; clk = 1;
#10 in = 0; clk = 0;
#10 in = 0; clk = 1;
#10 in = 0; clk = 0;
#10 in = 1; clk = 1;
#10 in = 1; clk = 0;
#10 in = 1; clk = 1;
#10 in = 1; clk = 0;
#10 in = 1; clk = 1;
#10 in = 1; clk = 0;
#10 in = 1; clk = 1;
#10 in = 1; clk = 0;
#10 in = 1; clk = 1;
#10 in = 1; clk = 0;
#10 in = 1; clk = 1;
#10 in = 0; clk = 0;
end
initial
begin
$dumpfile("finals_nake_ins.vcd");
$dumpvars();
$finish;
end
endmodule
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