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- An instruction pipeline has tive stages mely. instruction fetch (IF), instruction ecode and register fetch (ID/RF), instruction ocution (EX), memory access (MEM), and ester writeback (WB) with stage latencies I s 22 ns, 2 ns, I ns, and 0.75 ns, espectively (ns stands for nanoseconds). To pin in terms of frequency, the designers have decided to split the ID RF stage into threeConsider two different implementations of the same MIPS instruction set architecture. The instructions can be divided into three classes according to their CPI (R-type, I-type, J-type). P1 with a clock rate of 2.4 GHz and CPIs of 2, 3,and 4; and P2 with a clock rate of 2.8 GHz and CPIs of 3, 3, and 3. Given a program with a dynamic instruction count of 2.0E6 instructions divided into classes as follows: 25% R-type, 35% I-type, 40% J-type, which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.The results of the SPEC CPU2006 bzip2 benchmark running on an AMD Barcelona has an instruction count of 2.389E12, an execution time of 750 s, and a reference time of 9650 s. Find the SPECratio.
- For our simple 4-stage RISC pipeline, we run a particular benchmark program and find that it has 19% conditional branches. An additional 4% are unconditional branches. What is the maximum number of the conditional branches that could be taken if we want to keep the CPI to 1.10 or less? what is the minimum percentage of branch delay slots that need to be filled with useful instructions in order to keep the CPI to 1.0135? Assume that f2n= 0.25 ×f1n. In other words, whatever percentage of instructions need justa single NOP, there is another 25% of that requiring two NOPs.Implement the algorithm for MARIE architecture (e.g., Q3_MARIE.mas) A screenshot of the final execution states for a "test case" of your MARIE assembly code. Note your program needs to be general to take any input values using input instructions. However, a test input is used just to create a screenshot. (e.g., Q3_MARIE.PNG/JPG) The numbers of instructions in Q3_INSTRS.docx (Word document) Q3. Factorial (Iterative algorithm) - Use Q1 Get a user input of one non-negative integer numbers: A Calculate C is a factorial of A Print C Test case: A=4 Output should be 24Read the given scenario and answer questions based on 8086 microprocessor architecture. A programmer has written Assembly Language Program (ALP) using 8086 instruction set. The program will read any 200 user given inputs and process them to generate 200 outputs using stack. Each input and output is a byte length data. The input values are read from memory location D217H onward and the output values are stored from memory location E106H onward. The program uses a stack and the stack is defined from the memory location 54DAH and it can store 500 values. The program has 450 instructions stored from the memory location 6E20H to 713DH. The last instruction is HLT which is a byte long instruction. Identify the segments of the given memory locations Memory Location 6EEEH Code Segment Memory Location D2D0, Data Segment Memory Location 55A2H Stack Segment What will be the value of the Instruction Pointer (IP) when the program is about to execute the 449th instruction which is of a two address…
- The instruction pipeline of a RISC processor has the following stages. Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock eveles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instructions isConsider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor isSuppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
- Consider two different implementations of the same instruction set architecture. Th e instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is faster? a. What is the global CPI for each implementation? b. Find the clock cycles required in both cases.Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages, but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. What is the speed up achieved in this pipelined processor? 5In a perfectly balanced pipelined implementation, the time required to execute each individual instruction is same as for non-pipelined implementation. Select one: O True O False