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Figure 1 shows the design of a 6116 static CMOS RAM that can store 2K bytes of data. The memory has 16384 cells, arranged as a 128X128 memory matrix. The 11 address lines, which are needed to address 211 bytes of data, are divided into two groups. Lines A10 through A4 select one of the 128 rows in the matrix. Lines A3 through AO select 8 columns in the matrix at a time since there are 8 data lines. The data outputs from the matrix go through tri-state buffers before connecting to the data I/O lines. These buffers are disabled except when reading from the memory. Table 1 shows the truth table of the SRAM block. Model the 6116 SRAM block using VHDL. You should incorporate the timing specifications of the 6116 block in your VHDL model by looking at its datasheet. A10 Memory Matrix Row Decoder 128 X 128 A4 Column /0 Input Data Columa Decoder Control A3 Az Aj Ao OE D WE- Figure 1. Table 1. CS OE WE Mode VO pins Not selected Output disabled Read Write X High-Z High-Z Data out Data in X L L L L Now, assume that kn bit numbers are stored in a set of registers RO,R1,..Rk-1. Design a circuit that computes the arithmetic mean of the numbers in the registers. For large values of k , it is preferable to use an SRAM block with k rows andn columns, instead of using k registers. Model the mean computing circuit using VHDL. Write VHDL Code and please provide output images on ModelSim. ... ...

Figure 1 shows the design of a 6116 static CMOS RAM that can store 2K bytes of data. The memory has 16384 cells, arranged as a 128X128 memory matrix. The 11 address lines, which are needed to address 211 bytes of data, are divided into two groups. Lines A10 through A4 select one of the 128 rows in the matrix. Lines A3 through AO select 8 columns in the matrix at a time since there are 8 data lines. The data outputs from the matrix go through tri-state buffers before connecting to the data I/O lines. These buffers are disabled except when reading from the memory. Table 1 shows the truth table of the SRAM block. Model the 6116 SRAM block using VHDL. You should incorporate the timing specifications of the 6116 block in your VHDL model by looking at its datasheet. A10 Memory Matrix Row Decoder 128 X 128 A4 Column /0 Input Data Columa Decoder Control A3 Az Aj Ao OE D WE- Figure 1. Table 1. CS OE WE Mode VO pins Not selected Output disabled Read Write X High-Z High-Z Data out Data in X L L L L Now, assume that kn bit numbers are stored in a set of registers RO,R1,..Rk-1. Design a circuit that computes the arithmetic mean of the numbers in the registers. For large values of k , it is preferable to use an SRAM block with k rows andn columns, instead of using k registers. Model the mean computing circuit using VHDL. Write VHDL Code and please provide output images on ModelSim. ... ...

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Figure 1 shows the design of a 6116 static CMOS RAM that can store 2K bytes of data. The memory has 16384 cells, arranged as a 128X128 memory matrix. The 11 address lines, which are needed to address 211 bytes of data, are divided into two groups. Lines A10 through A4 select one of the 128 rows in the matrix. Lines A3 through A0 select 8 columns in the matrix at a time since there are 8 data lines. The data outputs from the matrix go through tri-state buffers before connecting to the data I/O lines. These buffers are disabled except when reading from the memory. Table 1 shows the truth table of the SRAM block. Model the 6116 SRAM block using VHDL. You should incorporate the timing specifications of the 6116 block in your VHDL model by looking at its datasheet. A10 Memory Matrix Row Decoder 128 X 128 A4 ... 107 Column I/0 Input Data Column Decoder Control A3 A2 A1 Ao OE D WE CS Figure 1. Table 1. CS OE WE Mode /0 pins X Not selected High-Z High-Z Data out X Output disabled Read Write L H H L H X Data in Now, assume that k n bit numbers are stored in a set of registers RO,R1,...Rk-1. Design a circuit that computes the arithmetic mean of the numbers in the registers. For large values of k, it is preferable to use an SRAM block with k rows and n columns, instead of using k registers. Model the mean computing circuit using VHDL. Write VHDL Code and please provide output images on ModelSim. ... ... ..
Transcribed Image Text:Figure 1 shows the design of a 6116 static CMOS RAM that can store 2K bytes of data. The memory has 16384 cells, arranged as a 128X128 memory matrix. The 11 address lines, which are needed to address 211 bytes of data, are divided into two groups. Lines A10 through A4 select one of the 128 rows in the matrix. Lines A3 through A0 select 8 columns in the matrix at a time since there are 8 data lines. The data outputs from the matrix go through tri-state buffers before connecting to the data I/O lines. These buffers are disabled except when reading from the memory. Table 1 shows the truth table of the SRAM block. Model the 6116 SRAM block using VHDL. You should incorporate the timing specifications of the 6116 block in your VHDL model by looking at its datasheet. A10 Memory Matrix Row Decoder 128 X 128 A4 ... 107 Column I/0 Input Data Column Decoder Control A3 A2 A1 Ao OE D WE CS Figure 1. Table 1. CS OE WE Mode /0 pins X Not selected High-Z High-Z Data out X Output disabled Read Write L H H L H X Data in Now, assume that k n bit numbers are stored in a set of registers RO,R1,...Rk-1. Design a circuit that computes the arithmetic mean of the numbers in the registers. For large values of k, it is preferable to use an SRAM block with k rows and n columns, instead of using k registers. Model the mean computing circuit using VHDL. Write VHDL Code and please provide output images on ModelSim. ... ... ..
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