Consider a system with 2-level cache, at 0.6 hit ratio in level 1 memory. The L1 memory is 4 times faster than L2. The average access time is increased by 40% from 50 ns. What is the of change in the hit ratio? percentage
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- If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?Assume that we have a paged memory system with a cache to hold the most active page table entries. It takes 20ns to search the cache. If the page table is normally held in memory, and memory access time is lus, what is the effective access time if the hit ratio is 85%? What hit ratio will be necessary to reduce the effective memory access time to 1.1µs?
- Suppose we have a processor with a base CPI of 2.0 assuming all references hit in the pnmary cache and a clock rate of 1000 MHz. The main memory access time is 100 ns. Suppose the miss rate per instruction is 5%. What is the revised CPI? How much taster will the machine run it we put a secondary cache (with 20-ns access time) that reduces the miss rate to memory to 2%On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?You are given the following data about a virtual memory system:(a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 9 msec.If page references are handled by the TLB 99% of the time, and only 0.01%lead to a page fault, what is the effective address-translation time?
- You are given the following data about a virtual memory system:(a)The TLB can hold 1024 entries and can be accessed in 1 clock cycle (1 nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 6 msec.If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, what is the effective address-translation time?An university student was trying improve the performance of one of the test computers. Computer initially had 2-way set associative mapping with 16kb cache and 128 KB byte addressable main memory with 256 bytes block size. It was later decided to change it to 4-way cache. Will there be an increase or decrease in tag directory size due to this change? By how much?.Q1. Consider that the up system consists of two memory sections, the SRAM and the EPROM. The up clock system is 5 MHz and the bus cycle is equal to 4-clocks of the system clock pulses. For reading process, suppose that the waiting time of SRAM equals % waiting time of EPROM. If you know that, the total time requires for reading both memory types 1900 ns, what is the total waiting time requires for reading 128 bytes from the SRAM and the total waiting time requires for reading 512 bytes of EPROM? How many wait states require for reading each section of memory? Sketch the required circuit for generating the required number of the wait states.
- The access time of the cache memory is 100ns and that of main memory 1000ns.It is estimated that S0percent of the memory requests are for read and the remaining 20 percent for write. The hit ratio for read accesses only is 0.9. A write through procedure is used. What is the average access time of the system considering only memory read cycles? What is the average access time of the system for both read cycles and write requests? What is the hit ratio taking into consideration the write cycles?Consider a computer with the following characteristics: total of 4 Mbyte of main memory; word size of 1 byte; block size of 8 bytes; and cache size of 32 Kbytes. For the main memory address of 3BBCAE, give the corresponding tag, cache set, and offset value for a two-way set-associative cache in HEX. You have to show your solution steps.(b) Consider a paging system with the page table stored in memory. If a memory referencetakes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,and 75% of all page references are found in the TLB, what is the effective memory referencetime? (Assume that it takes zero time to find an entry in the TLB if it is already present).