Consider a demand-paged computer system which was recently measured to deter- mine the utilisation of CPU and the paging disk to decide the degree of multipro- gramming. The results are shown in the figure below. Explain what is happening in each scenario and what actions an operating system can take. Scenario 1 Scenario 2 Scenario 3 40 20 ■CPU utilisation 60 Disk utilisation 80 100
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- Consider a disk drive specifications. with the following 16 surfaces, 512 tracks/surface, 512 sectors/ track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation?Consider a disk that rotates at 3600 rpm. The seek time to move the head between ad- jacent tracks is 2 ms. There are 32 sectors per track, which are stored in linear order from sector 0 through sector 31. The head sees the sectors in ascending order. Assume the read/write head is positioned at the start of sector 1 on track 8. There is a main memory buffer large enough to hold an entire track. Data is transferred between disk locations by reading from the source track into the main memory buffer and then writing the date from the buffer to the target track. a. How long will it take to transfer sector 1 on track 8 to sector 1 on track 9? b. How long will it take to transfer all the sectors of track 8 to the corresponding sec- tors of track 9?Consider a computer system that has the following characteristics: The memory bus runs at 400 MHz. The memory bus is 8 bytes wide. Accessing a memory address in memory requires 8 memory bus cycles. The disk drives can each read a block every 4 milliseconds. Disk blocks read are 8 kilobytes each. Assume Direct Memory Access from the disk drive. What is the highest percentage of the memory bus capacity that could be consumed by the disk’s Direct Memory Access if there are 4 disk drives in use?
- Consider a Disk I/O transfer, in which 1500 bytes are to be transferred, but number of bytes on a track is 1000, and rotation speed of disk is 1500 rps but the average time required to move the disk arm to the required track is 15 ms, then what will be total access time?For an old computing system with 2K bytes physical memory, and the virtual address has 13bits. Suppose that the size of page/frame is 256 bytes. For a process A, it has its codes and data inpage 0, 1, 2, 10, 11, 28, 29, where pages 0, 1, 10, 29 are in frame 1, 3, 4 and 6, respectively.Moreover, frame 0 contains kernel OS code/data and all other frames are free.a. Show the page table and the content of each PTE for process A;b. Use a figure to illustrate the address translation for virtual address 1110000100000 and explainwhat happens during the translation (interaction among page table, physical memory, disk, andoperating system);c. Suppose that there is a TLB with 4 entries and the current content has the mapping informationfor pages 0, 1. Draw a new figure to illustrate the translation of address 101000011000 andexplain what happens during the translation process.In this problem, you will explore processor frequency in the context of the speed of light. Suppose you have overclocked a processor to 8,722.78MHz. This processor can execute one instruction per cycle. Further let us suppose that the system is accessing a magnetic disk (HD) with an access time of 11ms. 1. Determine the number of instructions the CPU must pause when waiting for a read request for data from the HD to complete. 2. Suppose that you are designing the machine architecture and want to guarantee the CPU can obtain data from memory within 4 CPU cycles. Given that the address has to travel from the CPU to the memory unit (MMU) and that the data has to travel from memory to the CPU, what is the maximum distance between CPU and the MMU if the signal on the memory bus propagates at 75% of the speed of light?
- Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk.?Consider a demand-paged computer system where the degree of multiprogramming is currently fixed at seven. The system was recently measured to determine utilization of the CPU and the paging disk. Three alternative results are shown below. For each case, what is happening? Can the degree of multiprogramming be increased to increase the CPU utilization? Is the paging helping? Justify.a. CPU utilization 10 percent; disk utilization 95 percentb. CPU utilization 95 percent; disk utilization 1 percentc. CPU utilization 10 percent; disk utilization 5 percenSuppose the user process' size is 8192Kb and is a standard hard disk where swapping has a data transfer rate of 1Mbps. Calculate for the total swap time in milliseconds (swap-in time and swap-out time) of the 8192Kb process to and from the physical memory.
- Consider a computer system that uses virtual memory with paging (no TLB). Suppose main access time is 50 ns and no page faults. What is the effective memory access time (express in ns)Suppose a processor has access to three levels of memory. Level 1 has an access timeof 9 microseconds, level 2 has an access time of 23 microseconds and level 3 has anaccess time of 65 microseconds. Level 1 contains a subset of the bytes contained inlevel 2, and level 2 contains a subset of the bytes contained in level 3. It is estimatedthat 35 % of all requested bytes are contained in level 1, 68 % of all requested bytesare contained in level 2 and 100 % of all requested bytes are contained in level 3. If abyte to be accessed is in level 1, then the processor will directly access it from level 1.If a byte to be accessed is not in level 1 but in level 2, then the processor will directlyaccess it from level 2. If a byte to be accessed is not in level 1 and not in level 2, thenthe processor will directly access it from level 3. For simplicity, we assume that theaccessed bytes are not transferred between the memory levels. Moreover, we ignorethe time that is required for the processor to…A computer has instructions that each require two bus cycles, one to fetch the instruc- tion and one to fetch the data. Each bus cycle takes 10 nsec and each instruction takes 20 nsec (i.e., the internal processing time is negligible). The computer also has a disk with 2048 512-byte sectors per track. Disk rotation time is 5 msec. To what percent of its normal speed is the computer reduced during a DMA transfer if each 32-bit DMA transfer takes one bus cycle?