Consider a computer with byte-addressable main memory of size 8 GB and page size of 1 KB. Assume a process P has a virtual address space from 0 to 3653 (decimal). Determine the width of the virtual address , the width of the page #field and the width of the offset field (Note: enter only the numbers e.g. 8 for 8 bits etc.)
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- Assume variables have logical addresses with 16-bit page numbers and 16-bit offset using the memory configuration below. (Note that each hexidecimal is 4 bits long and Ox means hexadecimal radix) Logical Address Format Page Table Physical Memory Physical Address (starting) Oxppppdddd Page Frame Frame Size (hex) Size (dec) Ox10000 Ox10000 2 Охс000 65536 PPpp: page number dddd: page offset 1 1 Оxd000 65536 3 2 Охе000 Ox10000 65536 3 Oxf000 Ox10000 65536 Translate the following addresses: What is the physical address for 0x00011119 What is the physical address for 0x00000001 What is the logical address for Oxd0000001 ? What is the logical address for Oxc0000002 ?Assume variables have logical addresses with 16-bit page numbers and 16-bit offset using the memory configuration below. (Note that each hexidecimal is 4 bits long and Ox means hexadecimal radix) Logical Address Format Physical Memory Physical Address (starting) Page Table Охрppdddd Page | Frame Frame Size (hex) Size (dec) 2 Охс000 Ox10000 65536 pppp: page number dddd: page offset 1 1 Оxd000 Ox10000 65536 3 2 Охе000 Ox10000 65536 3 Oxf000 Ox10000 65536 Translate the following addresses: What is the physical address for 0x0002ffff What is the physical address for Ox0000abcd ? What is the logical address for Oxf000000f ? What is the logical address for Oxc000bbcc ?Assume variables have logical addresses with 16-bit page numbers and 16-bit offset using the memory configuration below. (Note that each hexidecimal is 4 bits long and Ox means hexadecimal radix) Logical Address Format Physical Memory Physical Address (starting) Page Table Size (dec) 65536 65536 Frame Size (hex) Oxppppdddd Page Frame 2 Ox10000 Ox10000 Охс000 pppp: page number dddd: page offset 1 1 Oxd000 2 Охе000 Ox10000 65536 3 Oxf000 Ox10000 65536 Translate the following addresses: What is the physical address for 0x0002ffff ? What is the physical address for 0x0000abcd ?
- Given the following: Logical Memory size of 1000 Physical Memory size of 2000 Page (and frame) size of 100 Block A contains data for a program Select Block A’s size and its starting point in both memories. Then write the page table for Block A based on your selections. See below for the layout of both memories and an example of Block A of size 200. Logical Memory Physical Memory location/ page location/frame 0 to 99/ 0 0 to 99/ 0 100 to 199 /1 Block A 100 to 199/ 1 200 to 299/ 2 Block A 200 to 299/ 2 300 to 399/ 3 300 to 399/ 3 400 to 499/ 4 400 to 499/ 4 500 to 599/ 5 500 to 599/ 5 600 to 699/ 6 600 to 699/ 6 700 to 799/ 7 700 to 799/ 7 800 to 899/ 8 800 to 899/ 8 900 to 999/ 9 900 to 999/ 9 1000 to 1099/ 10 1100 to 1199/ 11 1200 to 1299/ 12 1300 to 1399/ 13 Block A 1400 to 1499/ 14 Block…Consider a program consists of five segments: S0 = 600, S1 = 14 KB, S2= 100 KB, S3 =580 KB and S4 = 96 KB. Assume at that time, the available free space partitions of memory are 1200–1805, 50 – 150, 220-234, and 2500-3180.Find the following:a. Draw logical to physical maps and segment table?b. Allocate space for each segment in memory?c. Calculate the external fragmentation and the internal fragmentation?d. What are the addresses in physical memory for the following logical addresses: 0.580, (b) 1.17 (c) 2.66 (d) 3.82 (e) 4.20?Create a program in C++ which simulates a direct cache. The memory array that contains the data to becached is byte addressable and can contain 256 single byte entries or lines. The cache has only 8 entriesor lines. The Data field in each line of the cache is 8 bits. Since the data stored in each line of the cache isonly 8 bits, there is no need for a line field. Only a tag field is needed which is log2(256) = 8 bits.The memory array can be filled with any values of your choice. The program should work by taking userinput of a memory address (index). This input represents the memory data that should be cached.Check the cache to see if the item is already cached. If it is not, your program should counta cache miss, and then replace the item currently in the cache with the data from the inputted address.Allow the user to input addresses (in a loop), until they so choose to end the program. The program should output the number of cache misses upon ending.
- Create a program in C++ which simulates a direct cache. The memory array that contains the data to be cached is byte addressable and can contain 256 single byte entries or lines. The cache has only 8 entries or lines. The Data field in each line of the cache is 8 bits. Since the data stored in each line of the cache is only 8 bits, there is no need for a line field. Only a tag field is needed which is log2(256) = 8 bits. The memory array can be filled with any values of your choice. The program should work by taking user input of a memory address (index). This input represents the memory data that should be cached. Your program will check the cache to see if the item is already cached. If it is not, your program should count a cache miss, and then replace the item currently in the cache with the data from the inputted address. Allow the user to input addresses (in a loop), until they so choose to end the program. The program should output the number of cache misses upon ending.ADD [R1], R2, [R3]; Here [R1] and [R3] indicate memory locations pointed by R1 and R3 register respectively. Here the operand field next to opcode will hold the result at the end. Assume that the machine code of this instruction is loaded at address 1020H of the main memory. Also assume that the contents of registers R1, R2 and R3 are 2001H, 2002H and 2003H respectively. Moreover, 1000H, 2000H and 3000H are saved at memory addresses 2001H, 2002H and 2003H respectively. a) Draw a schematic diagram of a CPU, show its important functional units required to process this instruction.Design a memory map to work with 8085 Microprocessor to have 8K byte ROM and 2K byte RAM. ROM should start from memory location 0000H and RAM immediately follows it. Use exhaustive decoding scheme?
- ., which contains temporary data (such as 7. A process generally also includes the process . function parameters, return addresses, and local variables), and a contains global variables. which ..... stack / data section heap / data section stack / code section heap / data sectionPart A For each byte sequence listed, determine the Y86 instruction sequence it encodes. If there is some invalid byte in the sequence, show the instruction sequence up to that point and indicate where the invalid value occurs. For each sequence, the starting address, then a colon, and then the byte sequence are shown. 0x100: 30f3fcfffff40630008000000000000 0x100: 30f3fcfffffff irmovq $-4,%rbx Ox10a: 40630008000000000000 | rrmovq %rsi,0×80A(%rcx) O0x115: 00 halt Ox100: 30f3fcffffffff irmovq $-4,%rbx Ox10a: 40630008000000000000 | rmmovq %rsi,0x800(%rbx) Ox114: 00 halt 0x100: 30f3fcfffffffff rrmovq $-8,%rbx Ox109: 40630008000000000000 | rmmovq %rsi,0x800(%rbx) 0x200: a06f800c020000000000000030f30a00000000000000 0x113: 00 halt 0x100: 30f3fcffffffffff irmovq $-4,%rbx 0x200: a06f pushq %rsi 0x10a: 40630008000000000000 | rmmovq %rsi,0x800(%rbx) Ox202: 800c02000000000000 call proc Ox116: 00 halt 0x20b: 00 halt 0x20c: proc: Submit Request Answer 0x20c: 30f30a00000000000000 | irmovq $10,%rbx…Suppose a computer using direct mapped cache has 224 bytes of byte- addressable main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. (Note: 64K = 26 * 210) a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?