architecture MY STRUCT of COMB LOGIC 15 signal c1, C2: STD LOGIC; component AND port (10,11:in STD LOGIC; 0:0ut STD LOGIC); end component; component OR port (10,11:in STD LOGIC; 0:out STD LOGIC); end component; component NOR port (I0:in STD LOGIC; 0:out STD LOGIC): end component; begin Ul: AND port map (A(1), A(0), c1): U2: OR port map (A(3), A(2), C2); U3: NOR port map (c1, C2, B); end COMB LOGIC;
architecture MY STRUCT of COMB LOGIC 15 signal c1, C2: STD LOGIC; component AND port (10,11:in STD LOGIC; 0:0ut STD LOGIC); end component; component OR port (10,11:in STD LOGIC; 0:out STD LOGIC); end component; component NOR port (I0:in STD LOGIC; 0:out STD LOGIC): end component; begin Ul: AND port map (A(1), A(0), c1): U2: OR port map (A(3), A(2), C2); U3: NOR port map (c1, C2, B); end COMB LOGIC;
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Transcribed Image Text:architecture MY STRUCT of COMB LOGIC is
signal C1, C2: STD LOGIC;
component AND port (10,11:in STD LOGIC; 0:0ut STD LOGIC):
end component;
component OR port (10, 1l:in STD LOGIC; 0:out STD LOGIC);
end component;
component NOR port (I0:in STD LOGIC; 0:out STD LOGIC)
end component;
begin
01: AND port map (A(1), A(0), c1):
U2: OR port map (A (3), A(2), C2);
U3: NOR port map (C1, C2, B);
end COMB LOGIC;
Figure Qla.
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