(a) Draw a NAND logic diagram that implements the complement of the following function: F (A, B, C, D)=Σ(0, 1, 2, 3, 6, 10, 11, 14), and (b) repeat for a NOR logic diagram.
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(a) Draw a NAND logic diagram that implements the complement of the following function: F (A, B, C, D)=Σ(0, 1, 2, 3, 6, 10, 11, 14), and (b) repeat for a NOR logic diagram.
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- DISCUSSION: 1- Design the logic eircuit for the following conditions and draw the output wave form, X is a 0 if any two of the three variables A, B, and C are 1, X is al for all other conditions. 2- Implement the following function with only AND and NOT gates, F-AB+AB+BC W-XY (XZ+XY Z+ Y Z) + XZ 3- Use NAND gate, NOR gate, or combinations of both to implement the following expression:- a) X-A [B + C (D +E)] b) X B (CDE+EF G) (A B+ C) 4-a) What is the applications of AND gate and OR gate? b) In OR gate why 1 +1 1? c) The Fig. (1-12 ) shows the A & B inputs and the output is C, For the OR gate using the A and B inputs of Fig. (1-12) draw the C output for each of the following: The AND gate. • The NAND gate. • The NOR gate. .The EX-OR gate. • The EX-NOR gate. 1-12Q#01: The schematic shown in figure below is for Divide_by_11, a frequency divider, that divides clk by 11 and asserts its output for one cycle. The unit consists of a chain toggle-type flip-flops with additional logic to form an output pulse every 11th pulse of clk. The asynchronous signal rst is active-low and drives Q to 1. Develop and verify a model of Divide_by_11. Vcc 20LSB Q2 03MSB clk clk clk clk clk rst rst rst rst wl w2 clk QB cik_by_11 rst rstImplement the following Boolean function F, using the two level forms of logic (a) NAND-AND, (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR: F (A, B, C, D)=Σ(0, 4, 8, 9, 10, 11, 12, 14)
- EXERCISES 1. Construct various basic logic gates with CMOS NAND gate. 2. If one of the two inputs of a NAND gate is connected to "1", it will act as a NOT gate. What happens if one input is connected to "0"? MULTIPLE CHOICE QUESTIONS () 1. The output F of a NAND gate is equal to: 1. A+B 2. AB 3. A+B ( ) 2. Which of the followings can be used to construct a NOT gate? ( )3. is equivalent to which of the followings? 2-11d) A SR flip-flop is connected as shown in Figure Q3d(i). i) ii) Identify the input excitation expression, S and R for the SR flip-flop. Construct the output waveform Q of the flip-flop circuit for the given waveform shown in Figure Q3d(ii). The output Q='0' initially. Ignore the SET and CLR inputs. CLOCK A B CLOCK D D S SET R CLR Q Figure Q3d(i) Q Figure Q3d(ii) (5 marke)Design a logic circuit with inputs from four signal lines: A, B, C, and D, representing a 4-bit binary number (A as MSB and D as LSB). The circuit should output high only if the binary input is less than 7 (0111;). Construct the circuit using only NAND gates.
- 5. Simplify the following function using K-Map and draw logic diagram for that. E(A, B,CD)=Em(0,1,2,3,4,5,7,8,10,11,12,13,14,15). Choose the best answer that completes the statement or answers the question. 1. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? a) AND or OR gates b) XOR or XNOR gates c) NOR or NAND gates 2. In S-R flip-flop, ifQ= 0 the output is said to be d) AND or NOR gates a) Set b) Reset c) Previous state d) Current state 3. What is one disadvantage of an S-R flip-flop? a) It has no Enable input c) It has no clock input b) It has a RACE condition d) Invalid State 4. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fn) to the first flip-flop is 32 kHz, the output frequency (fou) is a) 1 kHz 5. In D flip-flop, D stands for a) Distant b) 2 kHz c) 4 kHz d) 16 kHz b) Data c) Desired d) Delay 6. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs? a) The output increases by 1 c) The output word increases by 2 b) The output decreases by 1 d) The output word…Implement the following Boolean function F, using the two-level forms of logic (a) NAND- AND, (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR: F(A, B, C, D) = E (0, 4, 8, 9, 10, 11, 12, 14) %3|
- 1. Build an electronic circuit for (A.B)->C a)if you have only electronic gate NAND b)if you have electronic gates TRUE, FALSE, AND,OR,NAND 2. Design the logic diagram for the input and output of F + FA + FB +FC + F(TK)positive-asserted reset negative-asserted set D Q (a) You are given a D flip-flop with positive-asserted reset input (left). Complete the following waveform diagram. CLK R D Q X (b) You are given a D flip-flop with negative-asserted set input (right). Complete the following waveform diagram: CLK SD 0Design a sequential circuit with input M and output A using the given state diagram. Reduce the number of states if necessary. Implement the circuit using SR flip-flops. Notes: Use chronological binary assignment for the states (e.g., state A = 0000, B = 0001, D = 0010 etc.) Use Q1, Q2, Q3, Q4 etc. as flip-flop variables where Q1 holds the MSB. 1/0 1/0 0/1 0/0 d. 0/0 e 1/0 1/1 1/1 b 0/1 a 1/1 1/1 0/0 0/1 0/1 f 0/0 0/0 1/1 h 1/1 0/1 1. The input equation to SR flip-flop, RQ2 = 2. The input equation to SR flip-flop, SQ3 = 3. The input equation to SR flip-flop, RQ3 = 4. The output equation A = 1/0