Question 21A CPU is equipped with a cache; Accessing a word takes 20 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache.What should be the hit ratio if the effective memory access time is 8 clock cycles?O 95%O 70%O None of themO 80%O 90%Question 22A CPU is equipped with a cache; Accessing a word takes 20 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache.What is the effective memory access time in clock cycles if the hit ratio is 90%?O 6.5O 6.4O None of themO 6.3O 6.2

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A CPU is equipped with a cache; Accessing a word takes 20 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache. What should be the hit ratio if the effective memory access time is 8 clock cycles? 95% O 70% None of them 80% - 90% Question 22 A CPU is equipped with a cache; Accessing a word takes 20 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache. What is the effective memory access time in clock cycles if the hit ratio is 90%? O 6.5 O 6.4 None of them 6.3 6.2

A CPU is equipped with a cache; Accessing a word takes 20 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache. What should be the hit ratio if the effective memory access time is 8 clock cycles? 95% O 70% None of them 80% - 90% Question 22 A CPU is equipped with a cache; Accessing a word takes 20 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache. What is the effective memory access time in clock cycles if the hit ratio is 90%? O 6.5 O 6.4 None of them 6.3 6.2

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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用Reac Crar Consider the diagram below that shows the fetching data flow for an indirect cycle along with the content of some memory addresses. What will be the content of the MAR register after finishing the execution of the indirect cycle for the instruction "ADD (750)" that uses indirect addressing mode? CPU MAR Memory Control unit Address Content 220 750 340 900 750 340 MBR 900 860 Address Data Control bus bus bus Select one: О 900 O 220 O 750 O 340 O860 ONone of the mentioned cholces is correct, 在