22. Use a 2-to-4 decoder, NAND gates, and edge-triggered D flip-flops to design a 4-bit shift register module that has the following function table. Draw a logic diagram for your module. S1 SO Mode Shift right (all four bits) Shift-left (all four bits) Synchronous common clear Synchronous parallel load 1 1 1 1
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- d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.The waveforms in Figure 08 are applied to the 4-bit parity logic. Determine the output wave-form in proper relation to the inputs. For how many bit times does even parity occur, and how is it indicated? The timing diagram includes eight bit times. Q.21 Bit time Ao A1 A2 A3 FIGURE 08(b) For a gated S-R latch. determine the Q output for the inputs in the following Figure. Show it in proper relation to the enable input, also draw the input waveforms on your answer script. Assume that Q starts LOW. EN S R Minimize the combinational logic circuit in the following figure using Karnaugh's map only. Inverters for the complemented variables are not shown. Q2.
- Problem 5 For the logic circuits shown below: determine the output F, write the true table, and draw the output F in proper relation to the given inputs with a timing diagram. a) A B F F 1. b) 1. F 1. CWhat are ways to speed up ripple adders? Mark all that apply. Use faster logic gates. a. Eliminate the output carry. b. Use the principle of carry lookahead. C. Use only multiplexers. d. None of the others are ways to speed up ripple adders. е. Lf. Design for the specific length of the input binary numbers.Q1. What is the difference between half and full adders? Draw and explain the circuit diagram to show the the addition of two binary numbers 1101 and 1001. Use one half adder and three full adders. Q2. Minimize the combinational logic circuit in the following figure using Karnaugh's map only. Inverters for the complemented variables are not shown. てS てっ二
- 3a) Show the truth table for JK flipflop for positive edge clock triggering. 3b) if for time period T=1ms, level triggering clock signal changes as 10111 then show the output for the input, D=01001(Use D flipflop)3c) Make a 6-bit serial register.Problem Statement: You design a circuit of a decade counter that will count from 0-9 only. You will only be using the following: (a) Button – only 1 button will be used to trigger the counting. (b) Flip flop IC to used as counting circuit with 4 - BITS binary OUTPUT. (c) IC's for Decoding the Binary OUTPUT of Flip-flops to Decimal Output (d) 7- Segment Display to display the OUTPUT from 0-9. Block Diagram: 4 Bit Binary Flip-Flop 7-Segment Display Button Decoder Circuits CircuitsThis question is from the subject Digital Logic Design. Assume your register number FA19BSExxx (excluding the dashes -) is in Hexadecimal, where xxx are the three digits of your registration number. a) Represent your registration number in the binary. b) Split the ten digits of your registration into two Hexadecimal numbers M and N, where the left most five digits make number M and the right most five digits make number N. Using r’s complement, subtract N from M. In other words, calculate M – N. Solve the question for registration no SP20-BCS-156.
- Design a sequential circuit (overlapping) with an input ‘x’. The pattern to be detected is the binary number that is equal to 01100 For this circuit:Draw the logic circuit for the datapath.Implement the function, W using ONE 4-to-1 multiplexer and other logic gates. b) Implement the function, X using ONE 4-to-1 multiplexer and other logic gates. Implement the function, Y using TWO 4-to-1 multiplexer and other logic gates. d) Implement the function, Z using ONE 8-to-1 multiplexer and other logic gates. Table Q1 ВCD Braille A B D W Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A ololO14.) Using rising edge JK-Flipflops and Digital Logic Gates, build a 4-Stage Shift Register. I recommend labeling D0, Q0, Q1, etc. Based on the waveforms for the CLK (clock) and D0 input generate the waveforms for Q0, Q1, Q2, Q3. DO CLK QO Q1 Q2 Q3