1. Times taken by major hardware units in a MIPS processor are: Memory read or write Register file read and write 100ps 40ps 70ps 70ps ALU Add unit All other hardware, including the control and multiplexers, has negligible delays. Then, a. What is the maximum clock frequency for a five-stage MIPS pipeline datapath? b.Compare this datapath with a single cycle datapath:

1. Times taken by major hardware units in a MIPS processor are: Memory read or write Register file read and write 100ps 40ps 70ps 70ps ALU Add unit All other hardware, including the control and multiplexers, has negligible delays. Then, a. What is the maximum clock frequency for a five-stage MIPS pipeline datapath? b.Compare this datapath with a single cycle datapath:

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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A common bus in a computer connects 16 source registers (each register is 32 bits) and one memory unit with word size of 32 bits also. If the bus is designed using multiplexers, answer the following: • What is the minimum number of multiplexers required? What is the minimum number of select lines each multiplexer has? If the bus is designed with three-state buffers and decoders, answer the following: • What is the minimum number of three-state buffers required? • What is the minimum number of decoders required? • What is the minimum size of each decode
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