1) Let us consider a logic system represented by the two Boolean functions: f(x₁, x2, x3, x4) = [(4,5, 10, 11, 12, 13, 14, 15) g(x₁, X2, X3, X4) = Σ(0, 1, 4, 5, 8, 9, 11, 12, 13, 15) 2) complete the following VHDL code using modelsim to describe the two Boolean functions using the conditional when/else statement:
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- Simplify the following Boolean function F, together with the don't care d. Using K-map and Draw the logic diagram. a) F (A,B,C,D) = Em(0,6,8,13,14) & d (2,4,10) %3D b)F (A,B,C,D) = Em(1,3,8,10,15) & d (0,2,9) %3DSimplify the following Boolean functions using K-Map and Design the Logic diagram. a) F (A,B,C) = Em(0,1,2,4,7) b) F (A,B,C,D) = m(1,3,9,11,12,13,14,15) c) F (A,B,C,D) = Em(3,7,11,13,14,15) %3D %3DGiven the below terms of the logic expression. F(A, B, C, D) = (2,4,7,10,12); d(A, B, C, D) = (0,6,8) 1. Obtain the KMAP to get minterms and maxterms. 2. Provide the Simplified Boolean Function. (Example: F = A) 3. Generate the Logic Diagram of the Simplified Boolean Function.
- 5. Simplify the following function using K-Map and draw logic diagram for that. E(A, B,CD)=Em(0,1,2,3,4,5,7,8,10,11,12,13,14,15)Please design a 6:1 multiplexer following the below procedures with data inputs of D5, D4, D3,D2, D1, D0 and output of Y.1 How many select signals are needed for this Mux.2) List a truth table for this Mux. Note: for all the unused combinations of select signals, Y=D53) Develop an optimized function for this Mux.4) Sketch the logic diagram of implementing this 6:1 Mux.5) Write a complete VHDL structural model to implement the above 6:1 multiplexer. Assume allthe required sub-component (standard gates) VHDL models are given/known that you can useDraw the equivalent logic circuit diagram of the following expressions : a. XY = F b. X + Y = F XÝZ = F c. d. XY + XZ = F e. XYZ + XÝZ = F
- Consider the design of two logic circuits that both have four inputs: A, B, C and D; and one output: X. Each circuit is implemented using 4-input AND gates (with negated inputs) and an OR gate to generate the output. For circuit 1, X is defined to be 1 if and only if the binary representation of A, B, C and D is even. Note A is the most significant bit, then B, then C, and Dis the least significant. For circuit 2, X is defined to be 1 if and only if the total number of 1's among A, B, C and D is even. Which of the following 4-input gates would be used in the implementation of both circuits?Please design a 6:1 multiplexer following the below procedures with data inputs of D5, D4, D3,D2, D1, D0 and output of Y.1 How many select signals are needed for this Mux.2) List a truth table for this Mux. Note: for all the unused combinations of select signals, Y=D5Develop an optimized function for this Mux.4Sketch the logic diagram of implementing this 6:1 Mux. Write a complete VHDL structural model to implement the above 6:1 multiplexer. Assume allthe required sub-component (standard gates) VHDL models are given/known that you can use.Boolean Function F(A,B,C,D) = { m (1,2,5,8,11,15), don't cares d(A,B,C,D) = { m (3,10) a. Using a K-map simply F in S.O.P. form b. Draw the logic circuit c. Using a K-map simply F in P.O.S. form d. Draw the logic circuit e. Which form has a lower gate input cost?
- File name: Mystery.asm In this exercise, you will be creating a 4-variable K-map to minimize the logic for the truth table below. From the minimized K- map, please write the HDL code using standard, built-in chips, such as (And, Not, Or, XOr, Mux, DMux). BCD Out 00000 OO100 0100 0 O1100 B0000 30011 1011 : 1011 B110 01. Given the Boolean expression (b + d)(a’+ b’ + c),a. Convert the expression to the other standard form. What do you call this standard form?b. Derive its canonical form. What do you call this canonical form?c. Derive the other canonical form. What do you call this canonical form?d. Provide the truth table of the expressione. Draw the logic circuit diagrams of the 2 standard forms- The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates. - Set up the circuits you designed with NAND and NOR gates and observe the outputs. Show the output values by drawing a table, applying all possibilities to the input values.