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25 #1
I am not sure how to understand how this works, could you explained in detail please?
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- Q#01: The schematic shown in figure below is for Divide_by_11, a frequency divider, that divides clk by 11 and asserts its output for one cycle. The unit consists of a chain toggle-type flip-flops with additional logic to form an output pulse every 11th pulse of clk. The asynchronous signal rst is active-low and drives Q to 1. Develop and verify a model of Divide_by_11. Vcc 20LSB Q2 03MSB clk clk clk clk clk rst rst rst rst wl w2 clk QB cik_by_11 rst rstIV) Convert Decimal to Hexadecimal (a) 974510 (b) 2976.5410 V) Convert from Binary to Hexadecimal (a) 10010110101012 (b) 111011101.010101012 VI) Convert from Hexadecimal to Binary (a) 7CAB516 (b) AF2.12B16a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)
- Assuming even parity, find the parity bit for each of the following data units. a. 1001010 b. 0001101 c. 1000000 d. 1110111Convert the 8-bit compressed code 00111010 to 12 bits PCM linear code.a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.) 1/6 Pat DigClock Part List OFFTIME = SuS DSTM1 ONTIME = DELAY= STARTVAL = 0 OPPVAL = 1 Sus EUK FleStim AC Lbrajes Design Cache b) Read the specification of 74LS47 (BCD-to-7-Segment Decoder shown in Appendix) to see how the logic IC operates to drive a 7-segment LED display. Draw the circuit connection of the decade counter in (a) and the decoder to display the count value on the 7-segment LED display. Further explain why common anode…
- Question 4 a) The IEEE Standard 754 representation of a floating point number is given as: 01101110110011010100000000000000. Determine the binary value represented by this number. b) Convert each of the following hexadecimal values to binary. i) AB1916 ii) 2DEF16 iii) 8A4516 iv) 9B5A16 c) If a computer's system clock is 2.4 GHz, calculate the period of the system clock. d) If an 8-bit binary number is used to represent an analog value in the range from 200 ounces to 700 ounces, what is the resolution of the system?parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.Add the following unsigned binary numbers. a. 10101 + 1010 b. 101011011 c. 1111+1111 d. 11100+ 1110 e. 11001+ 10011 f. 111011+101001
- Add the following BINARY NUMBERS 100010111.10111+ 101100001.110101What will be the state of a MOD64 counter after 90 input pulses if the starting state=000000?A.100100B.011010C.010110D.011100 2.A MOD 32 counter is holding the count 101112. What will the count be after 31 clock pulses?A.10100B.10010C.10000D.10110Up/Down State Machine Cousider a state machine implementation of a two bit up/down counter mput: up/doun, and two outputs: Outo and Out,, which also indicate the next state. When up/dowTI is high, the counter counts up (00,01,10,11,00, ). When up/doun is low, the counter counts down (00,11.10.01.00, ..). The state machine has one Part A Complete the state diagram below by adding all required transition arcs with input annotations. Output annotations are not required since they correspond to the new state. state state 00 01 state state 10 11