1- Write the VHDL code for the circuit shown in figure2. The circuit acts assupport circuit for the control unit. It takes 5 bit from a 7 bit bus and startcounting down at the rising Busedge of each clock cycle incase the "Decr" signal is active.A new data loaded to the(4.0)n shift count5-bit down counterCLKDecrcircuit each time the "Ld"signal activated. The output"n" is equal to "1" in case thecount value reaches "00000".Explain why the control unitLdn 04.00n-0needssuchcircuit.Dofunctional simulation for your design.Figure 2

The concrete RTN for shr relies upon a 5 bit register to hold the shift count. It must load,…

Write the VHDL code for the circuit shown in figure2. The circuit acts as support circuit for the control unit. It takes 5 bit from a 7 bit bus and start counting down at the rising Bus edge of each clock cycle in case the "Decr" signal is active. A new data loaded to the circuit each time the "Ld" (4.0) n shift count 5-bit down counter CLK Decr Ld n-04.00 signal activated. The output "n" is equal to "1" in case the count value reaches "00000". Explain why the control unit needs such circuit. n-0 Do functional simulation for your design. Figure 2 D-

Write the VHDL code for the circuit shown in figure2. The circuit acts as support circuit for the control unit. It takes 5 bit from a 7 bit bus and start counting down at the rising Bus edge of each clock cycle in case the "Decr" signal is active. A new data loaded to the circuit each time the "Ld" (4.0) n shift count 5-bit down counter CLK Decr Ld n-04.00 signal activated. The output "n" is equal to "1" in case the count value reaches "00000". Explain why the control unit needs such circuit. n-0 Do functional simulation for your design. Figure 2 D-

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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you need to design and draw a 3-bit synchronous binary up/down counter for experiment 5. You need to add a bit named "M" for the excitation table that helps it switch between up and down mode and draw the state transition diagram, excitation table, k-map and circuit diagram with T-flip flops. When M = 0, it will perform up counter. When M = 1, it will perform down counter.
Write a Verilog HDL of an eight-bit arithmetic logic unit (ALU). The circuit has a three-bit select bus (Sel), two sixteen-bit input datapaths, an eight-bit output (y) datapath and performs the arithmetic and logic operations listed below. Verify using a testbench.
Binary Counters Objective: Design, construct, and test a three-bit counter that counts up or down. A disable input D determines whether the counter is on or off. • If D=1, the counter is disabled and remains at its present count even thoughclock pulses are applied to the flip-flops. • If D-0, the counter is enabled and a second input, x, determines the directionof the count. • If x=1, the circuit counts the sequence 00, 01, 10,11 and the count repeats. • If x=0, the circuit counts the sequence 11, 10, 01, 00 and the count repeats. (Do not use D to disable the Clock) Note: Design the sequential circuit with D and x as inputs. Submission: Reports must include all schematics and cost of design. Compare your results with other solutions. (Costs, design....). Define why your design is better.
Part II: The purpose of this part is hardware implementation of the decoder 4to16 using decoder 2to4 Create a VHDL code of this circuit.
Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: an asynchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.
In verilog a counter must be developed from 0 to 9999 with a reset and parallel loading. The reset will be a button in charge of returning the count to 0 when pressed.For this practice, the implemented circuit will only use a 7-segment BCD converter module, which will have to be managed between the different 7-segment displays at a given frequency.
Part II: The purpose of this part is hardware implementation of the decoder 4to16 using decoder 2to4 Componen Create a VHDL code of this circuit.
11. Implement the given function f(A,B,C,D)=[(0,1,3,4,8,9,15)using 8:1 Multiplexer. 12. a. Design a control enabled JK FLIPFLOP using appropriate number of NAND gates. b.Determine the output of the given Positive edge triggered Flip flop .Assume the previous value of Q to be 0. Draw the output for the positions numbered from 1 to 5 at Q. CLK R 2
In digital electronics and modern computer hardware, a flip-flop is sequential digital circuit used as a basic memory element. It has two stable states and can be used to store state information. One of its states represents ‘1’ while the other represents ‘0’. The most common types of flip-flops are SR-flip-flop, JK-flip-flop, and D flip-flop. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs).
In digital electronics and modern computer hardware, a flip-flop is sequential digital circuit used as a basic memory element. It has two stable states and can be used to store state information. One of its states represents ‘1’ while the other represents ‘0’. The most common types of flip-flops are SR-flip-flop, JK-flip-flop, and D flip-flop. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). Figure 1 D-Flip-flop with clock pulse (CP) Figure 1 shows a D flip-flop with clock pulse (CP). D is directly passed from stage1 to stage 2 through NAND gate and passed as inverted through gate 5 and gate 4. The input D is always sampled when the system CP is 1. Considering the memory element in Figure 1, perform the following tasks: Design FSM for the Figure 1 Simulate the Figure 1 using C. Write 400 words report on shift and…
Q1: Design a Moore FSM to detect if an input sequence is divisible by 5. Each cycle a new bit comes as input towards LSB (e.g. if the current sequence is '1011' and the input is '0', the new sequence is '10110'). The FSM outputs a logic 1 if the sequence is divisible by 5, otherwise it outputs a logic 0. The starting point for the state diagram and a description of what the state does is depicted below. And assume initially the system is in state S0. a) Draw the Moore state diagram for this FSM using a minimum number of states. b) Draw the excitation table for the states. Define the states in order; e.g. S0 = 000, S1 = 001 etc. c) Write the minimum SOP Expression for all the bits of the states and the output 'O'. I: 0 so All 0 S1 Remainder 1
3. Implement a BCD to seven segment decoder for a common anode seven segment display. (It means that sending a 0 to a particular segment turns on and sending a 1 turns off the corresponding LED segment of the seven segment display). Use the variables A,B,C,D for the BCD inputs with 'A' as MSB. Use only 2-4 decoders and OR gates to implement the code converter. Don't use any other gates and/or components