is the way to faster execution. We talked about two different basic execution models that can support massively-parallel execution: MIMD and SIMD. One of the easiest ways to get some speedup by parallel processing is to simultaneously execute multiple copies of the same sequential program with different inpu

is the way to faster execution. We talked about two different basic execution models that can support massively-parallel execution: MIMD and SIMD. One of the easiest ways to get some speedup by parallel processing is to simultaneously execute multiple copies of the same sequential program with different inpu

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 26VE: _____ is a CPU design technique in which instruction execution is divided into multiple stages and...

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Suppose a program segment consists of a purely sequential part which takes 100 cycles to execute, and an iterated loop which takes 400 cycles per iteration. Assume that the loop is dependent on the sequential part, i.e., both parts cannot run in parallel. Also assume that the loop iterations are independent, and cannot be further parallelized. If the loop is to be executed 100 times, what is the maximum speedup possible using an infinite number of processors (as many processors as you could possibly need) compared to a single processor?
Floating Point operations are expensive mainly because they require a separate processing unit which requires overhead to work properly. For these and other reasons, some small processors don't support floating point arithmetic; only fixed point (each register has a "fixed" number of bits and the ALU only supports integer arithmetic). For example, if you were writing a program using a 16 bit processor and needed resolution of 1/32, your algorithm could use 5 "fractional" bits and 10 integer bits (1 bit is needed for the sign bit). Write how you would implement this in your program.
In MATLAB, a grey-scale image is stored a a matrix of numbers, all between 0 (black) and 255 (white). Since there are 256 possible values, 8 bits are needed or each pixel, in contrast to a normal integer, which is 64 bits.To save memory, grey-scale images are stored with a special data type, uint8 (unsigned 8-bit integer). In computer terminology, 8 bits = 1 byte. Even at one byte per pixel, a large image can consume a lot of memory. For example, a 1000x1000-pixel image takes 1 million bytes (which is a little less than 1 megabyte, since by convention 1 Mbyte = 2^20 bytes). One technique for reducing the size of an image is quantization - reducing the number of allowable levels from 256 to something smaller. Surprisingly, most images can be quantized by a large factor without losing much information. In this problem, you will quantize a grey-scale image to only 4 levels, so that it could (in principle) be stored as 2 bits per pixel. The template will read in an image file. Your job…
Write a small assembly language loop that calculates the arithmetic mean of an array. Let the array be called data points with n elements. You can use any assembly language you like, though it should be fairly RISC-like. Once you have that written, show how you can:•Reorder one instruction•Reorder two instructions•Try to reorder three instructions (or show why it's not possible) I know other students have posted similar questions and they are all answered, but those answers do not seem correct, so please do not copy from them
In general terms, CPUs are able to manipulate one or two pieces of data at a time. For instance, most CPUs have an instruction that essentially says "add A to B and put the result in C". The data for A, B and C could be—in theory at least—encoded directly into the instruction. Vector processors take this concept one step further. Instead of pipelining just the instructions, they also pipeline the data itself. a) How will you describe a vector processor? b) Instruction pipelining is an efficient way of decoding instructions. How does instruction pipelining reduce the amount of computing time as compared with traditional CPUs?
When it is feasible to do so, what are the advantages of moving the execution of the process to the input/output queue first? In the case that the input/output signal is broken, what do you believe will take place? Will this decrease the highest burst rate that the CPU is capable of achieving? What exactly do you mean by saying that? I'm not quite sure I get it.
Consider a program where 95% of the code can be parallelized. If you have aninfinite number of processors, what is the maximum speedup possible accordingto Amdahl's Law?
Assignment for Computer Architecture The assignment is to create a MIPS program that demonstrates that the associative law fails in addition for floating point numbers (single or double precision). You only need to demonstrate it for single precision. Remember the associative law is a + (b + c) = (a + b) + c. The program’s output should look something like the following where the xxx’s are the numbers you chose. The resulting numbers may be different than mine depending on your choice of a, b, and c. Using a = xxx, b = xxx, and c = xxx a + (b + c) = 0 (a + b) + c = 1 The key is to have two of the number large (one positively and one negatively but equal in magnitude) floating point numbers and the third floating point number very small in comparison. As a side note, the associative law will also fail for multiplication for floating point numbers, but you do not need to demonstrate that. Please don't forget to include comments in this code
The eight great ideas in computer architecture are similar to ideas from other fields. Match the eight ideas from computer architecture, “Design for Moore’s Law”, “Use Abstraction to Simplify Design”, “Make the Common Case Fast”, “Performance via Parallelism”, “Performance via Pipelining”, “Performance via Prediction”, “Hierarchy of Memories”, and “Dependability via Redundancy” to the following ideas from other fields: a. Assembly lines in automobile manufacturing b. Suspension bridge cables c. Aircraft and marine navigation systems that incorporate Wind information d. Express elevators in buildings e. Library reserve desk f. Increasing the gate area on a CMOS transistor to decrease its switching time g. Adding electromagnetic aircraft catapults (which are electrically-powered as opposed to current steam-powered models), allowed by the increased power generation off ered by the new reactor technology h. Building self-driving cars whose control systems partially rely on existing sensor…
Write and simulate a MIPS assembly-language routine that: 1. Prints your group number, for example “Group 1”, 2. Computes the dot product of two vectors, A_vec and B_vec, as described in Lab 4 of the Lab Manual, 3. Stores the result at memory word DOTPROD, and 4. Prints the result preceded by the phrase: “The result of the dot product is: “. Your data segment should look like the following: .data group: .asciiz “\nGroup x” msg: .asciiz "\nThe result of the dot product is: " A_vec: .word x, 4, 20, 13, 3, 10, 5 B_vec: .word 4, 2, 1, 2, 5, 2, 4 n: .word 7 DOTPROD: .word 0 Replace each “x” with your group number.
Connect a 5*7 dot-matrix display to the 8051-microcontroller (Draw the schematic on paper). Then, display the content of variable NUMBER on the display, digit by digit every one second. for example if NUMBER=249, then "2" will be displayed for one second, after that digit "4" and finally digit "9" will be displayed for a whole second. Assume that the necessary lookup table exists in Memory at address OXF000.
I have a 128-bit computer where addresses are 128 bits wide. I want to implement virtual memory with paging for this computer, and I want to use a page size of 4KB. I will design it so that a page table consumes exactly one page. How many page table entries (PTEs) fit within a page?