What is the difference between a cache that is entirely associative and a cache that is directly mapped?
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What is the difference between a cache that is entirely associative and a cache that is directly mapped?
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- For a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?"Spatial locality" and "temporal locality" boost performance with caches. These two events benefit caches.By convention, a cache is named according to the amount of data it contains (ie., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 bits. 1. Calculate the total number of bits required to implement a 32 KiB cache with two-word blocks. 2. Calculate the total number of bits required to implement a 64 KiB cache with 16-word blocks. How much bigger is this cache than the 32 KiB cache described in Exercise (1) above? (Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.) 3. Explain why this 64 KiB cache, despite its larger data size, might provide slower performance than the first cache. 4. Generate a…
- Consider the distinction between an entirely associative cache and a directly mapped cache.Cache Mapping Technique 1. Suppose a computer usingdirect-mapped cache has 2 bytes of byte=addressable main memory and a cache of32 blocks, where each cache block contains 16 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag, block, and offset fields?c) To which cacheblock will the memory address 0x0DB63 map?2. Suppose a computer using fullyassociative cache has 2 bytes of byte-addressable main memory and a cache of128 blocks, where each cache block contains 64 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag and offset fields?c) To which cacheblock will the memory address 0x01D872 map?3. A 2-way set-associative cacheconsists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressingis used.a) Show the mainmemory address format that allows us to map addresses from…By convention, a cache is named according to the amount of data it contains (i.e., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 bits. (a) Calculate the total number of bits required to implement a 32 KiB cache with two-word blocks. (b) Calculate the total number of bits required to implement a 64 KiB cache with 16-word blocks. How much bigger is this cache than the 32 KiB cache described in Part a? (Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.)