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- 1. What is the modulo of the circuit below? 2. Make a table of the count sequence. 3. A BCD counter can assume____discrete state. 4. A BCD counter can divide its input frequency by____. 5. A four-bit binary counter contains the number 0100. Nine inpulse occur. The new counter state is_____. 6. Design a 4-bit down counter.numbers. a) 101010101101 b) 1110100-0101110 c) 10110 10010 (Note: give the full 9-bit result) Give the sign-magnitude binary form. Use fewest bits possible to represent decimal numbers a) +1710 = b) -1710= c) -12410= = Perform the following computations on the given unsigned binary a) +1710 = b) -1710 = c) -12410 = Convert to two's-complement binary form.please show work included 4. If a 6-bit binary number is used to represent an analog value in the range from -63 to 126, what is the accuracy of the system? In other words, if the binary number is incremented by one, how much change does it represent in the analog value?
- Determine the total time required to serially transfer the eight bits contained in waveform A of Figure the first to be transferred. The 1 MHz clock is used as reference. and indicate the sequence of bits. The left-most bit is Clock AQUESTION 3 a) One of Medium Scale Integrated (MSI) circuit application is to compare between two input binary quantities and generates outputs to indicate which one has the greater, equal, or lower magnitude. Design the circuit to compare between two 2-bit inputs, you may choose only one output. Justify your design. b) Design an encoder to perform number conversion between two different numbering systems.7. Given the following ASK signal (Note: vertical lines denote bit divisions): (single bit)) (Lower Voltage '0', Higher Voltage '1') (MSB on the left) A E a. m 1 t U d 10 M e -5 -10+ a) What is the resulting bit stream? b) What is the bit rate? c) What ASCII character was transmitted Time(ns) 160
- Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: a synchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.a) Multiply the binary numbers 01001111 (multiplicand) and 00000101 (multiplier) by using the directaddition method. b) in image c)in imagea) Design Binary Ripple Counter using D-flipflop. b) Design asynchronous 4-bit UP-Down counter.
- (a) Determine the worst-case delay of a 16-bit carry select adder. Assume tsetup = tsum = 2, and tcarry = tmux = 1. Compare this with the worst-case delay of a 16-bit ripple carry adder. (b) If each stage has 4 bits, what is minimum number of bits (N) do we need to have, in order for the carry-select adder to start showing less delay (when compared to a ripple-carry adder)? Assume tsetup = tsum = 2, and tcarry = tmux = 1.Assuming even parity, find the parity bit for each of the following data units. a. 1001010 b. 0001101 c. 1000000 d. 1110111parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.