4.4 When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get “broken” and always register a logical 0. This is often called a “stuck-at-0” fault. 4.4.1 [5] <§4.4> Which instructions fail to operate correctly if the MemToReg wire is stuck at 0? 4.4.2 [5] <§4.4> Which instructions fail to operate correctly if the ALUSrc wire is stuck at 0? 4.4.3 [5] <§4.4> Which instructions fail to operate correctly if the Reg2Loc wire is stuck at 0?
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4.4 When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get “broken” and always register a logical 0. This is often called a “stuck-at-0” fault.
4.4.1 [5] <§4.4> Which instructions fail to operate correctly if the MemToReg wire is stuck at 0?
4.4.2 [5] <§4.4> Which instructions fail to operate correctly if the ALUSrc wire is stuck at 0?
4.4.3 [5] <§4.4> Which instructions fail to operate correctly if the Reg2Loc wire is stuck at 0?
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- II. IMPLEMENTATION OF SIMPLE SYSTEMS. Implement the given RTL below using bus connection and multiplexers and/or tri-state buffers. Assume that the given control signals are all mutually exclusive, and all registers are 4-bit wide. You may include additional flip-flop pins if necessary. A: W + Z,V + 1(high) B: X + V,Z + V C: X +W,Y + 0 (low) D: V + Y,W + Y,z-Y E: Y + X,Z + XII. IMPLEMENTATION OF SIMPLE SYSTEMS. Implement the given RTL below using bus connection and tri-state buffers. Assume that the given control signals are mutually exclusive, and all registers are 4-bit wide. You may include additional flip-flop pins if necessary. V: c€ E, DEE W: DEB, E €1 (high) X: DEC, BEC, A€c Y: cEA, E E A Z: AD, B E0 (low)Q): For the circuit in Figure. write a sequence of instruction to poll switch at 16 of 74F244 that is connected to port 7. Include in the solution the steps required to get the address for the port 7 before writing polling instruction. 0286 UN ACK 19 ALE AD-AD MO DEN RO AD AD- CLK 747373 A3291 leth G 747245 Data but Tarecever bi-drections) DR 18 Ata Au 4 Demultiplexing A₂ A B C 747131 Input Output F₁ Addren decoder 0,0 P₁ Decoder 0-0- CLK 74F374 Cuput Patt DE 74F244 Input Pot Bufer Latch or buffer LED Voc Vbc Input/output
- Assignment1- Computer Organization The next table represents a truth table of a 1-bit comparator. With 3 outputs. A B A>B AB Comparator AProblems in this exercise assume that the logic blocks used to implement a processor's datapath (COD Figure 4.23) have the following latencies: Sign HMem/ Register D-Mem File 250 ps 150 ps Mux ALU Adder 25 ps 200 ps 150ps Single Register Register gate Read Setup 5 ps 30ps extend Control 50 ps 20 ps 50ps "Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. "Register setup" is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File. (a) Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in COD…Assignment1- Computer Organization The next table represents a truth table of a 1-bit comparator. With 3 outputs. A A>B AB Comparator B A(d) The table below shows the ALUcontrol signal of the datapath we discussed in class. Instruction Funct ALU Орсode ALUop ALU action operation field control Iw 00 load word XXXXXX add 0010 Sw 00 store word XXXXXX add 0010 beq 01 branch equal subtract 0110 XXXXXX R-type 10 add 100000 add 0010 R-type 10 subtract 100010 subtract 0110 R-type 10 AND 100100 AND 0000 R-type 10 OR 100101 OR 0001 R-type 10 set on less than 101010 set on less than 0111 You want to add the bne instruction into the datapath, which already includes the required hardware for the instruction. Write out the ALUop for bne and how you can determine whether the bne results in the branch to be taken.computer engineering: PLEASE HELP Design a 4-bit 2’s complement format adder/subtractor circuit that is also capable of indicating the occurrence of an overflow condition. The circuit has two 4-bit inputs, P and S, and a 1-bit input Op. The value of Op specifies whether the operation to be carried out is addition or subtraction. The outputs for the circuit are R (4-bit wide) and Ov (1-bit wide; Ov =1 indicates the occurrence of an overflow during the addition/subtraction process and Ov = 0 indicates that there is no overflow). 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Do not implement this in VHDL. int PredY(int x1, int y1, int x2, int y2, int xp) { int m, b, ynew; if (x1 – x2) <> 0 { m = (y1 - y2) / (x1 - x2); b = y1 - m * x1; ynew = m * xp + b; return(ynew); } else { return(65535); // that's a 16-bit FFFF } }Task 4.3 1. Using only the decoder and external gates, construct the following combinational circuit: a. 7-segment decoder (w,x,y,z) b. Two 2-bit comparator (A1, Bl1, A0, BO) c. Two 2-bit Adder (A1, B1, AO, BO) 2. Implement a full-adder circuit using multiplexerTask #2: A Binary-Coded Hexadecimal (BCH) converter accepts a 4-bit decimal input and displays the equivalent hexadecimal value on a 7-segment display. In this task, you will design a BCH converter and display its output on one of the 7-segment displays found on the DE1-SoC board. Consider the figure below. There are 4 ON/OFF switches {SW3, sw2, SWI, swo} that represent the 4-bit decimal input. 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