CSE_142_WI24_HW3

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142

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Computer Science

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May 17, 2024

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pdf

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CSE 142: Computer Architecture: A Software Perspective Winter 2024 Homework 3 Instructor: Leo Porter Due on: Tuesday, 13 February (32 points) Name: Date: Instructions Answer each problem in the boxes provided. Any writing outside of the boxes will NOT be graded. Do not turn in responses recorded on separate sheets. Handwritten or typed responses are accepted. In either case, make sure all answers are in the appropriate boxes. All responses must be neat and legible. Illegible answers will result in zero points. 1. Locality (2 point - Completeness ): For a 2-D array, the first index is the row, and the second index is the column. Assume each word is a 32 bit integer and the array is stored in row major order. Also assume that the variables i,j and sum are stored in registers: for (i=0; i<100; i++){ for(j=0; j<4000; j++){ sum+= a[j][i] + b[j][i]; } } It is observed that the above piece of code suffers from significant memory latency. Why do you think it has these large memory delays and how can we improve the code to reduce this?
2. Cache Basics (6 points - Correctness ): We want to explore three different 1024 byte cache designs: direct-mapped, 4-way set-associative, and fully- associative. All three caches have 64-byte block size and use 32-bit byte addressing. How many bits do you need to assign for the tag, index, and block offset field for the three different caches? Please write down the number of bits in the table below. Cache direct-mapped 4-way set-associative fully-associative block offset Index Tag
3. Cache Accesses (6 points - Correctness ): Complete the following table for each of the below cache configurations: (a) Cache size - 512 byte, 2-way set associative cache with 64-byte block size. (b) Cache size - 512 byte, fully associative cache with 64-byte block size. For each access fill the last column with the type of cache miss if it is a miss (Just write hit if it’s a cache hit). Use Least Recently Used (LRU) as the replacement policy. Show tag, index and offset bits calculation in the box below to get full credits. (You may use the empty space on the right side of the tables to keep track of the cache contents.) Cache (a) Cache (b) block offset Index Tag Sr. No. Address (in binary) Cache (a) (Type of Cache Miss) 1 0010 0110 0000 2 1101 1000 0100 3 0000 0110 0110 4 0101 1110 1010 5 1110 0100 1110 6 1010 0010 0000 7 0010 0110 0001 8 1011 1010 0011 9 1101 1000 1100 10 1000 1100 1100 11 1111 1010 0000 12 1011 1000 1011 13 0100 0000 1110 14 0111 1110 0010 15 0101 1111 1010 16 0111 1111 0011 17 1010 0000 0001 18 0010 0110 0001 19 1110 0110 0010 20 0100 0001 1000 21 1111 1010 1110 22 1011 1001 1011 23 1001 0011 1111 24 0101 1110 0010
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